View UPD17717GC-XXX-3B9_1483645.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

pd17717, 17718, 17719 mos integrated circuit document no. u12330ej2v0ds00 (2nd edition) date published july 2001 n cp(k) printed in japan the pd17717, 17718, and 17719 are 4-bit single-chip cmos microcontrollers containing hardware for digital tuning systems. provided with a wealth of hardware, these microcontrollers are available in many variations of rom and ram capacities to support various applications. therefore, a high-performance, multi-function digital tuning system can be configured with only one chip. in addition, a one-time prom model, pd17p719, which can be written only once and therefore is ideal for program evaluation and small-scale production of a pd17717, 17718, or 17719 system, is also available. features program memory (rom) abundant peripheral hardware units pd17717 : 24k bytes (12288 16 bits) general-purpose i/o ports, serial interfaces, a/d pd17718, 17719: 32k bytes (16384 16 bits) converter, d/a converter (pwm output), beep general-purpose data memory (ram) output, frequency counter pd17717, 17718: 1120 4 bits many interrupts pd17719 : 1776 4 bits external: 6 sources instruction execution time internal : 6 sources 1.78 s (with f x = 4.5-mhz crystal oscillator) power-on reset, ce reset, and power failure pll frequency synthesizer detection circuit dual modulus prescaler (130 mhz max.), supply voltage: v dd = 5 v 10 % programmable divider, phase comparator, charge pump ordering information part number package pd17717gc- -3b9 80-pin plastic qfp (14 x 14) pd17718gc- -3b9 80-pin plastic qfp (14 x 14) pd17719gc- -3b9 80-pin plastic qfp (14 x 14) remark indicates a rom code suffix. unless otherwise specified, the pd17719 is treated as the representative model in this document. 4-bit single-chip microcontrollers with dedicated hardware for digital tuning system the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. the mark shows major revised points. ? 1997 data sheet
pd17717, 17718, 17719 2 data sheet u12330ej2v0ds functional outline part number pd17717 pd17718 pd17719 item program memory (rom) 24k bytes (12288 16 bits) 32k bytes (16384 16 bits) general-purpose data memory (ram) 1120 4 bits 1776 4 bits instruction execution time 1.78 s (with f x = 4.5-mhz crystal oscillator) general-purpose port i/o port : 46 pins input port : 12 pins output port: 4 pins stack level address stack : 15 levels interrupt stack: 4 levels dbf stack : 4 levels (can be manipulated via software) interrupt external: 6 sources (falling edge of ce pin, int0 through int4) internal : 6 sources (timers 0 through 3, serial interfaces 2 and 3) timer 5 channels basic timer (clock: 10, 20, 50, 100 hz) : 1 channel 8-bit timer with gate counter (clock: 1 k, 2 k, 10 k, 100 khz) : 1 channel 8-bit timer (clock: 1 k, 2 k, 10 k, 100 khz) : 2 channels 8-bit timer multiplexed with pwm (clock: 440 hz, 4.4 khz) : 1 channel a/d converter 8 bits 6 channels (hardware mode and software mode selectable) d/a converter (pwm) 3 channels (8-bit or 9-bit resolution selectable by software) output frequency: 4.4 khz, 440 hz (with 8-bit pwm selected) 2.2 khz, 220 hz (with 9-bit pwm selected) serial interface 2 units (4 channels) 3-wire serial i/o mode, sbi mode, or 2-wire serial i/o/i 2 c note bus mode selectable 3-wire serial i/o/uart mode selectable pll frequency division mode direct division mode (vcol pin (mf mode) : 0.5 to 3 mhz) synthesizer pulse swallow mode (vcol pin (hf mode) : 10 to 40 mhz) (vcoh pin (vhf mode): 60 to 130 mhz) reference frequency 13 types selectable (1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 18, 20, 25, 50 khz) charge pump two error-out output pins (eo0, eo1) phase comparator unlock status detectable by program frequency counter intermediate frequency (if) measurement p1c0/fmifc pin: in fmif mode 10 to 11 mhz in amif mode 0.4 to 0.5 mhz p1c1/amifc pin: in amif mode 0.4 to 0.5 mhz external gate width measurement p2a1/fcg1, p2a0/fcg0 pin beep output 2 pins output frequency: 1 khz, 3 khz, 4 khz, 6.7 khz (beep0 pin) 67 hz, 200 hz, 3 khz, 4 khz (beep1 pin) note when the i 2 c bus mode is used (including when it is implemented in software without using the peripheral hardware), inform nec when you place an order for mask rom.
3 pd17717, 17718, 17719 data sheet u12330ej2v0ds part number pd17717 pd17718 pd17719 item reset power-on reset (on power application) reset by reset pin watchdog timer reset can be set only once on power application: 65536 instruction, 131072 instruction, or no-use selectable stack pointer overflow/underflow reset can be set only once on power application: interrupt stack or address stack selectable ce reset (ce pin low high level) ce reset delay timing can be set. power failure detection function standby clock stop mode (stop) halt mode (halt) supply voltage pll operation: v dd = 4.5 to 5.5 v cpu operation: v dd = 3.5 to 5.5 v package 80-pin plastic qfp (14 x 14)
pd17717, 17718, 17719 4 data sheet u12330ej2v0ds pin configuration (top view) 80-pin plastic qfp (14 x 14) pd17717gc- -3b9 pd17718gc- -3b9 pd17719gc- -3b9 22 gnd2 p0d3/ad3 p0d2/ad2 p0d1/ad1 p0d0/ad0 p1c3/ad5 p1c2/ad4 p1c1/amifc p1c0/fmifc v dd 1 vcoh vcol gnd1 eo0 eo1 test p1d3 p1d2 p1d1/beep1 p1d0/beep0 int2 p1a3/int4 p1a2/int3 p1a1 p1a0/tm0g p3a3 p3a2 p3a1 p3a0 p3b3 p3b2 p3b1 p3b0 p2a2 p2a1/fcg1 p2a0/fcg0 p1b3 p1b2/pwm2 p1b1/pwm1 p1b0/pwm0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p0c2 p0c3 p2c0 p2c1 p2c2 p2c3 p3d0 p3d1 p3d2 p3d3 p3c0 p3c1 p3c2 p3c3 p2b0 p2b1 p2b2 p2b3 int0 int1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 reset v dd 0 ce x in x out gnd0 reg p2d0/sb0 p2d1/sb1 p2d2/sck p0b0/si3/rxd p0b1/so3/txd p0b2/sck3 p0b3/si2 p0a0/so2 p0a1/sck2 p0a2/scl p0a3/sda p0c0 p0c1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
5 pd17717, 17718, 17719 data sheet u12330ej2v0ds pin name ad0-ad5 : a/d converter input amifc : am frequency counter input beep0, beep1 : beep output ce : chip enable eo0, eo1 : error-out output fcg0, fgc1 : frequency counter gate input fmifc : fm frequency counter input gnd0-gnd2 : ground 0 to 2 int0-int4 : external interrupt input pwm0-pwm2 : d/a converter output p0a0-p0a3 : port 0a p0b0-p0b3 : port 0b p0c0-p0c3 : port 0c p0d0-p0d3 : port 0d p1a0-p1a3 : port 1a p1b0-p1b3 : port 1b p1c0-p1c3 : port 1c p1d0-p1d3 : port 1d p2a0-p2a2 : port 2a p2b0-p2b3 : port 2b p2c0-p2c3 : port 2c p2d0-p2d2 : port 2d p3a0-p3a3 : port 3a p3b0-p3b3 : port 3b p3c0-p3c3 : port 3c p3d0-p3d3 : port 3d reg : cpu regulator reset : reset input rxd : uart serial data input sb0, sb1 : sbi serial data i/o sck : sbi serial clock i/o sck2, sck3 : 3-wire serial clock i/o scl : 2-wire serial clock i/o sda : 2-wire serial data i/o si2, si3 : 3-wire serial data input so2, so3 : 3-wire serial data output test : test input tm0g : timer 0 gate input txd : uart serial data output vcoh : local oscillation high input vcol : local oscillation low input v dd 0, v dd 1 : power supply x in , x out : main clock oscillation
pd17717, 17718, 17719 6 data sheet u12330ej2v0ds block diagram 4 4 ad0/p0d0 ad5/p1c3 ad1/p0d1 ad2/p0d2 ad3/p0d3 ad4/p1c2 4 4 4 4 4 4 4 3 4 4 3 4 4 4 p0a0-p0a3 p0b0-p0b3 p0c0-p0c3 p0d0-p0d3 p1a0-p1a3 p1b0-p1b3 p1c0-p1c3 p1d0-p1d3 p2a0-p2a2 p2b0-p2b3 p2c0-p2c3 p2d0-p2d2 p3a0-p3a3 p3b0-p3b3 p3c0-p3c3 p3d0-p3d3 pwm2/p1b2 pwm0/p1b0 pwm1/p1b1 port a/d converter d/a converter 8-bit timer3 basic timer rf ram 1120 4 bits ( pd17717, 17718) 1776 4 bits ( pd17719) sysreg alu instruction decoder rom 12288 16 bits ( pd17717) 16384 16 bits ( pd17718, 17719) program counter stack vcoh vcol eo0 eo1 pll so2/p0a0 sck2/p0a1 scl/p0a2 sda/p0a3 si2/p0b3 sck3/p0b2 so3/txd/p0b1 si3/rxd/p0b0 beep0/p1d0 beep1/p1d1 int0 int1 int2 int3/p1a2 int4/p1a3 fcg0/p2a0 fcg1/p2a1 fmifc/p1c0 amifc/p1c1 tm0g/p1a0 x in x out ce reset v dd 0, v dd 1 reg v cpu cpu peripheral gnd0-gnd2 serial interface2 serial interface3 beep interrupt control frequency counter 8-bit timer0 gate counter 8-bit timer1 8-bit timer2 osc reset regulator sb0/p2d0 sb1/p2d1 sck/p2d2
7 pd17717, 17718, 17719 data sheet u12330ej2v0ds contents 1. pin functions ................................................................................................................ .............. 11 1.1 pin function list ........................................................................................................... ....... 11 1.2 equivalent circuits of pins ................................................................................................. 16 1.3 connections of unused pins .............................................................................................. 21 1.4 cautions on using ce, int0 through int4, and reset pins .......................................... 23 1.5 cautions on using test pin .............................................................................................. 23 2. program memory (rom) ......................................................................................................... .24 2.1 outline of program memory ............................................................................................... 24 2.2 program memory .............................................................................................................. ... 25 2.3 program counter ............................................................................................................. .... 26 2.4 flow of program ............................................................................................................. ..... 26 2.5 cautions on using program memory ................................................................................ 29 3. address stack (ask) .......................................................................................................... ...... 30 3.1 outline of address stack .................................................................................................... 30 3.2 address stack register (asr) ........................................................................................... 30 3.3 stack pointer (sp) .......................................................................................................... ...... 32 3.4 operation of address stack ............................................................................................... 33 3.5 cautions on using address stack ..................................................................................... 34 4. data memory (ram) ............................................................................................................ ....... 35 4.1 outline of data memory ...................................................................................................... 35 4.2 configuration and function of data memory .................................................................... 37 4.3 data memory addressing ................................................................................................... 40 4.4 cautions on using data memory ....................................................................................... 41 5. system registers (sysreg) ................................................................................................... 4 2 5.1 outline of system registers ............................................................................................... 42 5.2 system register list ........................................................................................................ ... 43 5.3 address register (ar) ....................................................................................................... .44 5.4 window register (wr) ........................................................................................................ 46 5.5 bank register (bank) ........................................................................................................ .47 5.6 index register (ix) and data memory row address pointer (mp: memory pointer) ......................................................................................................... 4 8 5.7 general register pointer (rp) ............................................................................................ 50 5.8 program status word (psword) ...................................................................................... 52 6. general register (gr) ........................................................................................................ .... 54 6.1 outline of general register ................................................................................................ 5 4 6.2 general register ............................................................................................................ ...... 54 6.3 generating address of general register by each instruction ........................................ 55 6.4 cautions on using general register ................................................................................. 55
pd17717, 17718, 17719 8 data sheet u12330ej2v0ds 7. alu (arithmetic logic unit) block ............................................................................................ .56 7.1 outline of alu block ....................................................................................................... ... 56 7.2 configuration and function of each block ....................................................................... 57 7.3 alu processing instruction list ........................................................................................ 57 7.4 cautions on using alu ....................................................................................................... 61 8. register file (rf) ......................................................................................................... ............... 62 8.1 outline of register file .................................................................................................... ... 62 8.2 configuration and function of register file ..................................................................... 63 8.3 control registers ........................................................................................................... ...... 64 8.4 port input/output selection registers ............................................................................... 76 8.5 cautions on using register file ........................................................................................ 80 9. data buffer (dbf) .......................................................................................................... ............. 81 9.1 outline of data buffer ...................................................................................................... .... 81 9.2 data buffer ................................................................................................................. .......... 82 9.3 relationships between peripheral hardware and data buffer ........................................ 83 9.4 cautions on using data buffer ........................................................................................... 86 10. data buffer stack ......................................................................................................... ......... 87 10.1 outline of data buffer stack ............................................................................................... 87 10.2 data buffer stack register ................................................................................................. 87 10.3 data buffer stack pointer .................................................................................................. .89 10.4 operation of data buffer stack .......................................................................................... 90 10.5 using data buffer stack .................................................................................................... .. 91 10.6 cautions on using data buffer stack ................................................................................ 91 11. general-purpose port ...................................................................................................... .... 92 11.1 outline of general-purpose port ........................................................................................ 92 11.2 general-purpose i/o port (p0a, p0b, p0c, p1d, p2a, p2b, p2c, p2d, p3a, p3b, p3c, p3d) ................................................................................................................. .... 95 11.3 general-purpose input port (p0d, p1a, p1c) ................................................................... 109 11.4 general-purpose output port (p1b) .................................................................................. 112 12. interrupt ................................................................................................................. .................... 113 12.1 outline of interrupt block ................................................................................................. .. 113 12.2 interrupt control block .................................................................................................... ... 115 12.3 interrupt stack register ................................................................................................... ... 129 12.4 stack pointer, address stack registers, and program counter .................................... 133 12.5 interrupt enable flip-flop (inte) ....................................................................................... 133 12.6 accepting interrupt ........................................................................................................ ...... 134 12.7 operations after interrupt has been accepted ................................................................. 139 12.8 returning from interrupt routine ....................................................................................... 139 12.9 external interrupts (ce and int0 through int4 pins)....................................................... 140 12.10 internal interrupts ....................................................................................................... ......... 143
9 pd17717, 17718, 17719 data sheet u12330ej2v0ds 13. timers ...................................................................................................................... ...................... 144 13.1 outline of timers .......................................................................................................... ....... 144 13.2 basic timer 0 .............................................................................................................. ......... 146 13.3 timer 0 .................................................................................................................... .............. 159 13.4 timer 1 .................................................................................................................... .............. 168 13.5 timer 2 .................................................................................................................... .............. 175 13.6 timer 3 .................................................................................................................... .............. 182 14. a/d converter ............................................................................................................... ............. 189 14.1 outline of a/d converter ................................................................................................... .. 189 14.2 input selection block ...................................................................................................... .... 190 14.3 compare voltage generation and compare blocks ........................................................ 192 14.4 comparison timing chart ................................................................................................... 1 95 14.5 using a/d converter ........................................................................................................ .... 196 14.6 cautions on using a/d converter ...................................................................................... 197 14.7 status at reset ............................................................................................................ ......... 197 15. d/a converter (pwm mode) .................................................................................................... . 198 15.1 outline of d/a converter ................................................................................................... .. 198 15.2 pwm clock selection register ........................................................................................... 199 15.3 pwm output selection block ............................................................................................. 200 15.4 duty setting block ......................................................................................................... ...... 203 15.5 clock generation block ..................................................................................................... . 207 15.6 d/a converter output wave ............................................................................................... 207 15.7 example of using d/a converter ....................................................................................... 210 15.8 status at reset ............................................................................................................ ......... 211 16. serial interface ............................................................................................................ ........... 212 16.1 outline of serial interface ................................................................................................ ... 212 16.2 serial interface 2 ......................................................................................................... ......... 214 16.3 serial interface 3 ......................................................................................................... ......... 282 17. pll frequency synthesizer ................................................................................................. 30 4 17.1 outline of pll frequency synthesizer .............................................................................. 304 17.2 input selection block and programmable divider ........................................................... 305 17.3 reference frequency generator ........................................................................................ 309 17.4 phase comparator ( -det), charge pump, and unlock ff ............................................. 311 17.5 pll disabled status ........................................................................................................ .... 315 17.6 using pll frequency synthesizer ..................................................................................... 316 17.7 status at reset ............................................................................................................ ......... 320 18. frequency counter ........................................................................................................... ..... 321 18.1 outline of frequency counter ............................................................................................ 321 18.2 input/output selection block and gate time control block ........................................... 322 18.3 start/stop control block and if counter ........................................................................... 325 18.4 using if counter ........................................................................................................... ....... 332 18.5 using external gate counter .............................................................................................. 33 4 18.6 status at reset ............................................................................................................ ......... 335
pd17717, 17718, 17719 10 data sheet u12330ej2v0ds 19. beep ........................................................................................................................ ........................ 336 19.1 outline of beep ............................................................................................................ ....... 336 19.2 i/o selection block and output selection block .............................................................. 337 19.3 clock selection block and clock generation block ........................................................ 339 19.4 output waveform of beep ................................................................................................. 340 19.5 status at reset ............................................................................................................ ......... 340 20. standby ..................................................................................................................... ................... 341 20.1 outline of standby function ............................................................................................... 3 41 20.2 halt function .............................................................................................................. .......... 342 20.3 clock stop function ........................................................................................................ .... 348 20.4 device operation in halt and clock stop status .............................................................. 350 20.5 cautions on processing of each pin in halt and clock stop status .............................. 350 20.6 device operation control function of ce pin .................................................................. 352 21. reset ....................................................................................................................... ....................... 355 21.1 outline of reset ........................................................................................................... ........ 355 21.2 ce reset ................................................................................................................... ............ 356 21.3 power-on reset ............................................................................................................. ...... 362 21.4 relationship between ce reset and power-on reset .................................................... 365 21.5 reset by reset pin ......................................................................................................... ... 369 21.6 wdt&sp reset ............................................................................................................... ..... 370 21.7 power failure detection .................................................................................................... .. 376 22. instruction set ............................................................................................................. ............ 381 22.1 outline of instruction set ................................................................................................. ... 381 22.2 legend ..................................................................................................................... ............. 382 22.3 instruction list ........................................................................................................... .......... 383 22.4 assembler (ra17k) embedded macro instruction ........................................................... 385 23. reserved symbols ............................................................................................................ ....... 386 23.1 data buffer (dbf) .......................................................................................................... ....... 386 23.2 system registers (sysreg) .............................................................................................. 386 23.3 port registers ............................................................................................................. ......... 387 23.4 register file (control registers) ........................................................................................ 38 9 23.5 peripheral hardware registers .......................................................................................... 394 23.6 others ..................................................................................................................... .............. 394 24. electrical characteristics ............................................................................................... 395 25. package drawing ............................................................................................................. ........ 398 26. recommended soldering conditions ............................................................................... 399 appendix a. cautions on connecting crystal resonator ........................................... 400 appendix b. development tools .............................................................................................. 401
11 pd17717, 17718, 17719 data sheet u12330ej2v0ds 1. pin functions 1.1 pin function list pin no. symbol function output form 1 int2 edge-detectable vectored interrupt input pins. rising or falling edge can be 41 int1 specified. 42 int0 2 p1a3/int4 port 1a multiplexed with external interrupt request signal input and event 3 p1a2/int3 signal input pins. 4 p1a1 p1a3 through p1a0 5 p1a0/tm0g 4-bit input port int4, int3 edge-detectable vectored interrupt tm0g input for gate of 8-bit timer 0 at reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained (p1a3 through p1a0) (p1a3 through p1a0) 6 p3a3 4-bit i/o port. cmos | | can be set in input or output mode in 4-bit units. push-pull 9 p3a0 at reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained 10 p3b3 4-bit i/o port. cmos | | can be set in input or output mode in 4-bit units. push-pull 13 p3b0 at reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained 14 p2a2 port 2a multiplexed with external gate counter input pins. cmos 15 p2a1/fcg1 p2a2 through p2a0 push-pull 16 p2a0/fcg0 3-bit i/o port can be set in input or output mode in 1-bit units. fcg1, fcg0 input for external gate counter at reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained (p2a2 through p2a0) (p2a2 through p2a0) (p2a2 through p2a0) (p2a2 through p2a0)
pd17717, 17718, 17719 12 data sheet u12330ej2v0ds pin no. symbol function output form 17 p1b3 port 1b multiplexed with d/a converter output pins. n-ch 18 p1b2/pwm2 p1b3 through p1b0 open-drain | | 4-bit output port (12 v) 20 p1b0/pwm0 pwm2 through p2m0 8- or 9-bit d/a converter output at reset with clock stopped power-on reset wdt&sp reset ce reset outputs low level outputs low level retained retained (p1b3 through p1b0) (p1b3 through p1b0) (p1b3 through p1b0) 21 gnd2 ground 33 gnd1 75 gnd0 22 p0d3/ad3 port 0d multiplexed with a/d converter input pins | | p0d3 through p0d0 25 p0d0/ad0 4-bit input port can be connected with pull-down resistor in 1-bit units. ad3 through ad0 analog input of a/d converter with 8-bit resolution at reset with clock stopped power-on reset wdt&sp reset ce reset input with pull-down input with pull-down retained retained resistor resistor (p0d3 through p0d0) (p0d3 through p0d0) 26 p1c3/ad5 port 1c multiplexed with a/d converter input and if counter input pins. 27 p1c2/ad4 p1c3 through p1c0 28 p1c1/amifc 4-bit input port 29 p1c0/fmifc ad5, ad4 analog input to a/d converter with 8-bit resolution fmifc, amifc input to frequency counter at reset with clock stopped power-on reset wdt&sp reset ce reset input input p1c3/ad5, p1c3/ad5, (p1c3 through p1c0) (p1c3 through p1c0) p1c2/ad4 p1c2/ad4 retained retained p1c1/amifc, p1c1/amifc, p1c0/fmifc p1c0/fmifc input input (p1c1, p1c0) (p1c1, p1c0) 30 v dd 1 power supply. supply the same voltage to these pins. 79 v dd 0 with cpu and peripheral function operating : 4.5 to 5.5 v with cpu operating : 3.5 to 5.5 v with clock stopped : 2.2 to 5.5 v
13 pd17717, 17718, 17719 data sheet u12330ej2v0ds pin no. symbol function output form 31 vcoh pll local oscillation (vco) frequency input. 32 vcol vcoh active with vhf mode selected by program; otherwise, pulled down. vcol active with hf or mw mode selected by program; otherwise, pulled down. because the input of these pins goes into an ac amplifier, cut the dc component of the input signal with a capacitor. 34 eo0 output from charge pump of pll frequency synthesizer. outputs the divided cmos 35 eo1 frequency of local oscillation and the result of comparison of the phase 3-state difference of reference frequency. at reset with clock stopped power-on reset wdt&sp reset ce reset high-impedance high-impedance high-impendance high-impedance output output output output 36 test test input pin. be sure to connect this pin to gnd. 37 p1d3 port 1d and beep output. cmos 38 p1d2 p1d3 through p1d0 push-pull 39 p1d1/beep1 4-bit i/o port 40 p1d0/beep0 can be set in input or output mode in 1-bit units. beep1, beep0 beep output at reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained ( p1d3 through p1d0) (p1d3 through p1d0) (p1d3 through p1d0) (p1d3 through p1d0) 43 p2b3 4-bit i/o port. cmos | | can be set in input or output mode in 1-bit units. push-pull 46 p2b0 at reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained 47 p3c3 4-bit i/o port. cmos | | can be set in input or output mode in 4-bit units. push-pull 50 p3c0 at reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained 51 p3d3 4-bit i/o port. cmos | | can be set in input or output mode in 4-bit units. push-pull 54 p3d0 at reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained
pd17717, 17718, 17719 14 data sheet u12330ej2v0ds pin no. symbol function output form 55 p2c3 4-bit i/o port. cmos | | can be set in input or output mode in 1-bit units. push-pull 58 p2c0 at reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained 59 p0c3 4-bit i/o port. cmos | | can be set in input or output mode in 1-bit units. push-pull 62 p0c0 at reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained 63 p0a3/sda ports p0a, p0b, and p2d are multiplexed with i/o of serial interface. n-ch 64 p0a2/scl p0a3 through p0a0 open-drain 65 p0a1/sck2 4-bit i/o port cmos 66 p0a0/so2 can be set in input or output mode in 1-bit units. push-pull 67 p0b3/si2 p0b3 through p0b0 68 p0b2/sck3 4-bit i/o port 69 p0b1/so3/ can be set in input or output mode in 1-bit units. txd p2d2-p2d0 70 p0b0/si3/ 3-bit i/o port rxd can be set in input or output mode in 1-bit units. 71 p2d2/sck sda, scl 72 p2d1/sb1 serial data and serial clock i/o of serial interface 2 in 2-wire serial i/o or n-ch 73 p2d0/sb0 i 2 c bus mode open-drain sck2, so2, si2 serial clock i/o, serial data output, and serial data input of serial interface 2 in 3-wire serial i/o mode sck3, so3, si3 serial clock i/o, serial data output, serial data input of serial interface 3 in 3-wire serial i/o mode txd, rxd serial data output and serial data input when uart of serial interface 3 is selected sck, sb1, sb0 serial clock and serial data i/o when sbi of serial interface 2 is selected at reset with clock stopped power-on reset wdt&sp reset ce reset input input retained retained p0a3 through p0a0, p0a3 through p0a0, p0a3 through p0a0, p0a3 through p0a0, p0b3 through p0b0, p0b3 through p0b0, p0b3 through p0b0, p0b3 through p0b0, p2d2 through p2d0 p2d2 through p2d0 p2d2 through p2d0 p2d2 through p2d0
15 pd17717, 17718, 17719 data sheet u12330ej2v0ds pin no. symbol function output form 74 reg cpu regulator. connect this pin to gnd via 0.1- f capacitor. 76 x out ground pins of crystal resonator. 77 x in 78 ce device operation-selection, ce reset, and interrupt signal input pin. device operation-select when ce is high, pll frequency synthesizer can operate. when ce is low, pll frequency synthesizer is automatically disabled internally. ce reset when ce goes high, device is reset at rising edge of internal basic timer setting pulse. this pin also has reset timing delay function. interrupt vectored interrupt occurs at falling edge of this pin. 80 reset reset input
pd17717, 17718, 17719 16 data sheet u12330ej2v0ds 1.2 equivalent circuits of pins (1) p0a (p0a1/sck2, p0a0/so2) p0b (p0b3/si2, p0b2/sck3, p0b1/so3/txd, p0b0/si3/rxd) p0c (p0c3, p0c2, p0c1, p0c0) p1d (p1d3, p1d2, p1d1/beep1, p1d0/beep0) p2a (p2a2, p2a1/fcg1, p2a0/fcg0) p2b (p2b3, p2b2, p2b1, p2b0) (i/o) p2c (p2c3, p2c2, p2c1, p2c0) p2d (p2d2/sck) p3a (p3a3, p3a2, p3a1, p3a0) p3b (p3b3, p3b2, p3b1, p3b0) p3c (p3c3, p3c2, p3c1, p3c0) p3d (p3d3, p3d2, p3d1, p3d0) note this is an internal signal that is output when the clock stop instruction is executed, and its circuit is designed not to increase the current consumption due to noise even if it is floated. v dd v dd ckstop note
17 pd17717, 17718, 17719 data sheet u12330ej2v0ds (2) p0a (p0a3/sda, p0a2/scl) (i/o) p2d (p2d1/sb1, p2d0/sb0) note this is an internal signal that is output when the clock stop instruction is executed, and its circuit is designed not to increase the current consumption due to noise even if it is floated. (3) p1b (p1b3, p1b2/pwm2, p1b1/pwm1, p1b0/pwm0) (output) (4) p0d (p0d3/ad3, p0d2/ad2, p0d1/ad1, p0d0/ad0) (input) note this is an internal signal that is output when the clock stop instruction is executed, and its circuit is designed not to increase the current consumption due to noise even if it is floated. v dd ckstop note v dd ckstop note a/d converter p0dpld flag high-on resistance
pd17717, 17718, 17719 18 data sheet u12330ej2v0ds (5) p1a (p1a1) (input) note this is an internal signal that is output when the clock stop instruction is executed, and its circuit is designed not to increase the current consumption due to noise even if it is floated. (6) p1c (p1c3/ad5, p1c2/ad4) (input) note this is an internal signal that is output when the clock stop instruction is executed, and its circuit is designed not to increase the current consumption due to noise even if it is floated. v dd ckstop note v dd a/d converter ckstop note
19 pd17717, 17718, 17719 data sheet u12330ej2v0ds (7) p1c (p1c1/amifc, p1c0/fmifc) (input) note this is an internal signal that is output when the clock stop instruction is executed, and its circuit is designed not to increase the current consumption due to noise even if it is floated. (8) ce reset int0, int1, int2 (schmitt trigger input) p1a (p1a3/int4, p1a2/int3, p1a0/tm0g) v dd v dd v dd v dd general-purpose port high-on resistance frequency counter ckstop note
pd17717, 17718, 17719 20 data sheet u12330ej2v0ds (9) x out (output), x in (input) (10) eo1, eo0 (output) (11) vcoh, vcol (input) v dd v dd high-on resistance high-on resistance v dd v dd high-on resistance internal clock high-on resistance x in x out v dd dwn up
21 pd17717, 17718, 17719 data sheet u12330ej2v0ds 1.3 connections of unused pins it is recommended to connect unused pins as follows: table 1-1. connections of unused pins (1/2) pin name i/o mode recommended connections of unused pins port pin p0d3/ad3-p0d0/ad0 input individually connect to gnd via resistor note 1 . p1c3/ad5 p1c2/ad4 p1c1/amifc note 2 set in port mode and individually connect to v dd or gnd p1c0/fmifc note 2 via resistor note 1 . p1a3/int4 individually connect to gnd via resistor note 1 . p1a2/int3 p1a1 p1a0/tm0g p1b3 n-ch open-drain set to low-level output by software and then open. p1b2/pwm2-p1b0/pwm0 output p0a3/sda i/o note 3 set in general-purpose input port mode by software and p0a2/scl individually connect to v dd or gnd via resistor note 1 . p0a1/sck2 p0a0/so2 p0b3/si2 p0b2/sck3 p0b1/so3/txd p0b0/si3/rxd p0c3-p0c0 p1d3 p1d2 p1d1/beep1 p1d0/beep0 p2a2 p2a1/fcg1 p2a0/fcg0 p2b3-p2b0 p2c3-p2c0 p2d2/sck p2d1/sb1 p2d0/sb0 notes 1. if a pin is externally pulled up (connected to v dd via resistor) or pulled down (connected to gnd via resistor) with a high resistance, the pin almost enters a high-impedance state, increasing the current (through-current) consumption of the port. generally, the resistance of a pull-up or pull- down resistor is several 10 k ? , though it depends on the application circuit. 2. do not set these pins as amifc and fmifc pins; otherwise, the current consumption will increase. 3. the i/o ports are set in the general-purpose i/o port mode at power-on reset, when reset by the reset pin, or when reset due to overflow or underflow of the watchdog timer or the stack.
pd17717, 17718, 17719 22 data sheet u12330ej2v0ds table 1-1. connections of unused pins (2/2) pin name i/o mode recommended connections of unused pins port pin p3a3-p3a0 i/o note 2 set in general-purpose input port mode by software and p3b3-p3b0 individually connect to v dd or gnd via resistor note 1 . p3c3-p3c0 p3d3-p3d0 pins other ce input connect to v dd via resistor note 1 . than port eo1 output open pins eo0 int0-int2 input individually connect to gnd via resistor note 1 . reset input connect to v dd via resistor note 1 . test directly connect to gnd. vcoh input disable pll via software and open. vcol notes 1. if a pin is externally pulled up (connected to v dd via resistor) or pulled down (connected to gnd via resistor) with a high resistance, the pin almost enters a high-impedance state, increasing the current (through-current) consumption of the port. generally, the resistance of a pull-up or pull- down resistor is several 10 k ? , though it depends on the application circuit. 2. the i/o ports are set in the general-purpose input port mode at power-on reset, when reset by the reset pin, or when reset due to overflow or underflow of the watchdog timer or the stack.
23 pd17717, 17718, 17719 data sheet u12330ej2v0ds 1.4 cautions on using ce, int0 through int4, and reset pins the ce, int0 through int4, and reset pins have a function to set a test mode in which the internal operations of the pd17719 are tested (ic test), in addition to the functions listed in 1.1 pin function list. when a voltage exceeding v dd is applied to any of these pins, the device is set in the test mode. if a noise exceeding v dd is superimposed during normal operation, therefore, the test mode is set by mistake, hindering the normal operation. especially if the wiring length of pins is too long, noise is superimposed on these pins. in consequence, the above problem occurs. therefore, keep the wiring length as short as possible to prevent noise from being superimposed. if superimposition of noise is unavoidable, connect an external component as illustrated below to suppress the noise. ? connect a diode with low v f connect a capacitor between a pin and v dd . between a pin and v dd . 1.5 cautions on using test pin when v dd is applied to the test pin, the device is set in the test mode. therefore, be sure to keep the wiring length of this pin as short as possible, and directly connect it to the gnd pin. if the wiring length between the test pin and gnd pin is too long, or if external noise is superimposed on the test pin, generating a potential difference between the test pin and gnd pin, your program may not run normally. ce, int0-int4, reset v dd ce, int0-int4, reset v dd diode with low v f v dd v dd gnd test short
pd17717, 17718, 17719 24 data sheet u12330ej2v0ds 2. program memory (rom) 2.1 outline of program memory figure 2-1 outlines the program memory. as shown in this figure, the addresses of the program memory are specified by the program counter. the program memory has the following two major functions. to store programs to store constant data figure 2-1. outline of program memory instruction constant data program memory program counter address specification
25 pd17717, 17718, 17719 data sheet u12330ej2v0ds 2.2 program memory figure 2-2 shows the configuration of the program memory. as shown in this figure, the pd17717 has 24k bytes (12288 x 16 bits) of program memory, and the pd17718 and 17719 have 32k bytes (16384 16 bits). therefore, the program memory addresses of the pd17717 are 0000h through 2fffh, and those of the pd17718 and 17719 are 0000h through 3fffh. because all instructions are one-word instructions , one instruction can be stored to one address of the program memory. as constant data, the contents of the program memory are read to the data buffer by using a table reference instruction. figure 2-2. configuration of program memory ( pd17718, 17719) 16 bits h h br addr instruction branch address br @ar instruction branch address call @ar instruction subroutine entry address movt dbf, @ar instruction table reference address address h h h h h h h h h h h h h h h h h h ( pd17717) reset start address serial interface 3 interrupt vector serial interface 2 interrupt vector timer 3 interrupt vector timer 2 interrupt vector timer 1 interrupt vector timer 0 interrupt vector int4 pin interrupt vector int3 pin interrupt vector int2 pin interrupt vector int1 pin interrupt vector int0 pin interrupt vector falling edge interrupt vector of ce pin segment 0 page 0 page 1 page 2 page 3 page 0 page 1 page 2 page 3 call addr instruction subroutine entry address call addr instruction subroutine entry address br addr instruction branch address segment 1 (system segment) 0 f 1 2 3 4 5 6 7 8 9 a b c f f f f 0 f 0 f 0 0 0 0 0 0 0 0 0 0 0 0 f f f f 0 f 0 f 0 0 0 0 0 0 0 0 0 0 0 0 7 f 7 f 0 f 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 2
pd17717, 17718, 17719 26 data sheet u12330ej2v0ds 2.3 program counter 2.3.1 configuration of program counter figure 2-3 shows the configuration of the program counter. as shown in this figure, the program counter consists of a 13-bit binary counter and a 1-bit segment register (sgr). bits 11 and 12 of the program counter indicate a page. the program counter specifies an address of the program memory. figure 2-3. configuration of program counter 2.3.2 segment register (sgr) the segment register specifies a segment of the program memory. table 2-1 shows the relationships between the segment register and program memory. the segment register is set only when the syscal entry instruction is executed. table 2-1. relationships between segment register and program memory value of segment register segment of program memory 0 segment 0 1 segment 1 2.4 flow of program the flow of the program is controlled by the program counter that specifies an address of the program memory. the program flow when each instruction is executed is described below. figure 2-5 shows the value that is set to the program counter when each instruction is executed. table 2-2 shows the vector address when an interrupt is accepted. 2.4.1 branch instruction (1) direct branch (?r addr? the branch destination address of the direct branch instruction is in the same segment of the program memory. in other words, a branch cannot be executed exceeding a segment. (2) indirect branch (?r @ar? the branch destination addresses of the indirect branch instruction are all the addresses of the program memory, i.e., addresses 0000h through 2fffh for the pd17717 and 0000h through 3fffh for the pd17718 and 17719. for further information, also refer to 5.3 address register (ar) . pc 0 sgr page pc pc 12 pc 11 pc 10 pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1
27 pd17717, 17718, 17719 data sheet u12330ej2v0ds 2.4.2 subroutine (1) direct subroutine call (?all addr? the first address of a subroutine that can be called by the direct subroutine instruction is in page 0 of each segment (addresses 0000h through 07ffh). (2) indirect subroutine call (call @ar) the first addresses of a subroutine that can be called by the indirect subroutine call instruction are all the addresses of the program memory, i.e., addresses 0000h through 2fffh for the pd17717 and 0000h through 3fffh for the pd17718 and 17719. for further information, also refer to 5.3 address register (ar). 2.4.3 table reference the addresses that can be referenced by the table reference instruction ( movt dbf, @ar ) are all the addresses of the program memory, i.e., addresses 0000h through 2fffh for the pd17717 and 0000h through 3fffh for the pd17718 and 17719. for further information, also refer to 5.3 address register (ar) and 9.2.2 table reference instruction (movt, dbf, @ar) . 2.4.4 system call the first address of a subroutine that can be called by the system call instruction ( syscal entry ) is the first 16 steps of each block (block 0 to 7) in page 0 of segment 1 (system segment). figure 2-4. outline of system call instruction page 1 page 2 page 3 page 0 (16 bits 2k steps) (16 bits 8k steps) segment 0 page 1 page 2 page 3 (16 bits 8k steps) segment 1 (system segment) block 0 block 1 block 2 block 7 block 0 of segment 1 entry address of syscal instruction 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 7 f 7 f 8 0 8 0 f f f f 0 0 0 0 f f f f 0 0 0 0 h h h h h h h h 0 0 0 0 0 0 0 0 2 2 3 3 2 3 3 2 7 f 7 f 8 0 8 0 f f f f 0 0 0 0 f f f f 0 0 0 0 h h h h h h h h 020ffh 02100h 021ffh 02200h 022ffh 02700h 02000h 0200fh area where entry address of system segment can be specified . . . .
pd17717, 17718, 17719 28 data sheet u12330ej2v0ds figure 2-5. value of program counter upon execution of instruction table 2-2. interrupt vector address order internal/external interrupt source vector address 1 external falling edge of ce pin 00ch 2 external int0 pin 00bh 3 external int1 pin 00ah 4 external int2 pin 009h 5 external int3 pin 008h 6 external int4 pin 007h 7 internal timer 0 006h 8 internal timer 1 005h 9 internal timer 2 004h 10 internal timer 3 003h 11 internal serial interface 2 002h 12 internal serial interface 3 001h contents of program counter (pc) sgr 1 0 0 b 12 0 0 1 1 0 0 0 b 11 0 1 0 1 0 0 0 b 10 0 b 9 0 b 8 0 b 7 0 0 b 6 0 0 b 5 0 0 b 4 0 0 b 3 0 b 2 0 b 1 0 b 0 0 program counter instruction br addr call addr syscal entry br @ar call @ar movt dbf, @ar ret retsk reti other instructions (including skip instruction) when interrupt is accepted power-on reset, watchdog timer reset, reset pin, ce reset page 0 page 1 page 2 page 3 entry l entry h operand of instruction (addr) operand of instruction (addr) contents of address register re- tained re- tained contents of address stack register (asr) (return address) specified by stack pointer (sp) vector address of each interrupt increment entry h : high-order 3 bits of entry entry l : low-order 4 bits of entry re- tained
29 pd17717, 17718, 17719 data sheet u12330ej2v0ds 2.5 cautions on using program memory 2.5.1 last address in each segment the segment register is not connected to the binary counter. therefore, address 0000h of segment 0 is specified next to address 1fffh, which is the last address of segment 0. to specify between segments, a dedicated instruction such as an indirect branch, indirect subroutine call, or system call instruction is used.
pd17717, 17718, 17719 30 data sheet u12330ej2v0ds 3. address stack (ask) 3.1 outline of address stack figure 3-1 outlines the address stack. the address stack consists of a stack pointer and address stack registers. the address of an address stack register is specified by the stack pointer. the address stack saves a return address when a subroutine call instruction is executed or when an interrupt is accepted. the address stack is also used when the table reference instruction is executed. figure 3-1. outline of address stack 3.2 address stack register (asr) figure 3-2 shows the configuration of the address stack register. the address stack register consists of sixteen 16-bit registers asr0 through asr15. actually, however, it consists of fifteen 16-bit registers (asr0 through asr14) because no register is allocated to asr15. the address stack saves a return address when a subroutine is called, when an interrupt is accepted, and when the table reference instruction is executed. stack pointer return address address stack register address specification
31 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 3-2. configuration of address stack register b 3 b 2 b 1 b 0 stack pointer (sp) b 3 sp3 b 2 sp2 b 1 sp1 b 0 sp0 b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 bit address stack register (asr) address 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh asr0 asr1 asr2 asr3 asr4 asr5 asr6 asr7 asr8 asr9 asr10 asr11 asr12 asr13 asr14 asr15 (undefined) cannot be used bit
pd17717, 17718, 17719 32 data sheet u12330ej2v0ds 3.3 stack pointer (sp) 3.3.1 configuration and function of stack pointer figure 3-3 shows the configuration and functions of the stack pointer. the stack pointer consists of a 4-bit binary counter. it specifies the address of an address stack register. a value can be directly read from or written to the stack pointer by using a register manipulation instruction. figure 3-3. configuration and function of stack pointer retained power-on reset wdt&sp reset ce reset clock stop name flag symbol b 3 s p 3 b 2 s p 2 b 1 s p 1 b 0 s p 0 address 01h read/write r/w stack pointer (sp) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 address 0 (asr0) address 1 (asr1) address 2 (asr2) address 3 (asr3) address 4 (asr4) address 5 (asr5) address 6 (asr6) address 7 (asr7) address 8 (asr8) address 9 (asr9) address 10 (asr10) address 11 (asr11) address 12 (asr12) address 13 (asr13) address 14 (asr14) setting prohibited specifies address of address stack register (asr) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 ( ( at reset ( ( ( ( ( ( power-on reset wdt&sp reset ce reset clock stop : reset by reset pin up on power application : reset by watchdog timer and stack pointer : ce reset : upon execution of clock stop instruction
33 pd17717, 17718, 17719 data sheet u12330ej2v0ds 3.4 operation of address stack 3.4.1 subroutine call instruction (?all addr? ?all @ar? and return instruction (?et? ?etsk? when a subroutine call instruction is executed, the value of the stack pointer is decremented by one, and the return address is stored to an address stack register specified by the stack pointer. when the return instruction is executed, the contents of the address stack register (return address) specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. 3.4.2 table reference instruction (?ovt dbf, @ar? when the table reference instruction is executed, the value of the stack pointer is incremented by one, and the return address is stored to an address stack register specified by the stack pointer. next, the contents of the program memory specified by the address register are read to the data buffer, the contents of the address stack register (return value) specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. 3.4.3 when interrupt is accepted and on execution of return instruction (?eti? when an interrupt is accepted, the value of the stack pointer is decremented by one, and the return address is stored to an address stack register specified by the stack pointer. when the return instruction is executed, the contents of an address stack register (return value) specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. 3.4.4 address stack manipulation instruction (?ush ar? ?op ar? when the push instruction is executed, the value of the stack pointer is decremented by one, and the contents of the address register are transferred to an address stack register specified by the stack pointer. when the pop instruction is executed, the contents of an address stack register specified by the stack pointer are transferred to the address register, and the value of the stack pointer is incremented by one. 3.4.5 system call instruction (?yscal entry? and return instruction (?et? ?etsk? when the syscal entry instruction is executed, the value of the stack pointer is decremented by one, and the return address and the value of the segment register are stored to an address stack register specified by the stack pointer. when the return instruction is executed, the contents of an address stack register (return value) specified by the stack pointer are restored to the program counter and segment register, and the value of the stack pointer is incremented by one.
pd17717, 17718, 17719 34 data sheet u12330ej2v0ds 3.5 cautions on using address stack 3.5.1 nesting level and operation on overflow the value of address stack register (asr15) is undefined when the value of the stack pointer is 0fh. accordingly, if a subroutine call or system call exceeding 15 levels, or an interrupt is used without manipulating the stack, execution returns to an undefined address. 3.5.2 reset on detection of overflow or underflow of address stack whether the device is reset on detection of overflow or underflow of the address stack can be specified by program. at reset, the program is started from address 0, and some control registers are initialized. this reset function is valid at power-on reset or reset by the reset pin. for details, refer to 21. reset .
35 pd17717, 17718, 17719 data sheet u12330ej2v0ds 4. data memory (ram) 4.1 outline of data memory figure 4-1 outlines the data memory. as shown in the figure, system registers, a data buffer, port registers, and port input/output selection registers are located on the data memory. the data memory stores data, transfers data with the peripheral hardware or ports, and controls the cpu. figure 4-1. outline of data memory (1/2) (a) pd17719 note port input/output selection registers are allocated to addresses 60h through 6fh of bank 15. peripheral hardware data transfer column address data memory bank0 port registers port registers port registers port registers bank1 bank2 bank3 bank4 bank14 bank15 note system registers ports 0123456789abcdef data transfer 0 1 2 3 4 5 6 7 data buffer ........ row address
pd17717, 17718, 17719 36 data sheet u12330ej2v0ds figure 4-1. outline of data memory (2/2) (b) pd17717, 17718 note port input/output selection registers are allocated to addresses 60h through 6fh of bank 15. cautions 1. the pd17717 and 17718 do not have banks 10 through 14. 2. nothing is allocated to addresses 00h through 5fh of bank15. peripheral hardware data transfer column address data memory bank0 port registers port registers port registers port registers bank1 bank2 bank3 bank4 bank9 bank15 note system registers ports 0123456789abcdef data transfer 0 1 2 3 4 5 6 7 data buffer row address ........
37 pd17717, 17718, 17719 data sheet u12330ej2v0ds 4.2 configuration and function of data memory figure 4-2 shows the configuration of the data memory. as shown in this figure, the data memory is divided into several banks with each bank made up of a total of 128 nibbles with 7h row addresses and 0fh column addresses. the data memory can be divided into five functional blocks. each block is described in 4.2.1 through 4.2.5 below. the contents of the data memory can be operated on, compared, judged, and transferred in 4-bit units with a single data memory manipulation instruction. table 4-1 lists the data memory manipulation instructions. 4.2.1 system registers (sysreg) the system registers are allocated to addresses 74h through 7fh. because the system registers are allocated to all banks, the same system registers exist at addresses 74h through 7fh of any bank. for details, refer to 5. system register (sysreg) . 4.2.2 data buffer (dbf) the data buffer is allocated to addresses 0ch through 0fh of bank 0. for details, refer to 9. data buffer (dbf) . 4.2.3 port registers the port registers are allocated to addresses 70h through 73h of banks 0 through 3. for details, refer to 11. general-purpose ports . 4.2.4 port input/output selection registers port input/output selection registers are allocated to addresses 60h through 6fh of bank15. for details, refer to 8.4 port input/output selection register . 4.2.5 general-purpose data memory the general-purpose data memory is allocated to the addresses of the data memory excluding those of the system registers, port registers, and port input/output selection registers. (a) pd17719 the general-purpose data memory of the pd17709 consists of a total of 1776 nibbles of the 112 nibbles each of banks 0 through 15 (bank15 only has 96 nibbles). (b) pd17717, 17718 the general-purpose data memory of the pd17707 and 17708 consists of a total of 1120 nibbles of the 112 nibbles each of banks 0 through 9.
pd17717, 17718, 17719 38 data sheet u12330ej2v0ds figure 4-2. configuration of data memory (1/2) (a) pd17719 note an identical system register exists. system registers bank0 data memory 0 1 2 3 4 5 6 7 0 bank1 column address 01 0 1 2 3 4 5 6 7 general registers system registers (sysreg) note example address 51h of bank 0 b 3 b 2 b 1 b 0 0 1 2 3 4 5 6 7 port register system registers (sysreg) note 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 system registers (sysreg) note system registers (sysreg) note 123456789abcdef bank2 bank14 bank15 23456789ab c def data buffer 0123456789ab c def 0123456789ab c def fixed to 0 column address fixed to 0 0123456789ab c def bank0 column address bank1-bank3 column address bank4-bank14 column address bank15 port register port input/output selection registers row address row address row address row address row address
39 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 4-2. configuration of data memory (2/2) (b) pd17717, 17718 note an identical system register exists. cautions 1. the pd17717 and 17718 do not have banks 10 through 14. 2. nothing is allocated to addresses 00h through 5fh of bank15. system registers bank0 data memory 0 1 2 3 4 5 6 7 0 bank1 column address 01 0 1 2 3 4 5 6 7 general registers system registers (sysreg) note example address 51h of bank 0 b 3 b 2 b 1 b 0 0 1 2 3 4 5 6 7 port register system registers (sysreg) note 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 system registers (sysreg) note system registers (sysreg) note 123456789abcdef bank2 bank9 bank15 23456789ab c def data buffer 0123456789ab c def 0123456789ab c def column address fixed to 0 0123456789ab c def bank0 column address bank1-bank3 column address bank4-bank9 column address bank15 port register fixed to 0 port input/output selection registers nothing is allocated row address row address row address row address row address
pd17717, 17718, 17719 40 data sheet u12330ej2v0ds table 4-1. data memory manipulation instructions function instruction operation add add addc subtract sub subc logic and or xor compare ske skge sklt skne transfer mov ld st judge skt skf 4.3 data memory addressing figure 4-3 shows address specification of the data memory. an address of the data memory is specified by a bank, row address, and column address. a row address and a column address are directly specified by a data memory manipulation instruction. however, a bank is specified by the contents of a bank register. for the details of the bank register, refer to 5. system register (sysreg) . figure 4-3. address specification of data memory data memory address bank register column address row address bank b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 instruction operand
41 pd17717, 17718, 17719 data sheet u12330ej2v0ds 4.4 cautions on using data memory 4.4.1 at power-on reset the contents of the general-purpose data memory are undefined at power-on reset. initialize the data memory as necessary. 4.4.2 cautions on data memory not provided if a data memory manipulation instruction that reads the data memory is executed to a data memory address not provided, undefined data is read. nothing is changed even if data is written to such an address.
pd17717, 17718, 17719 42 data sheet u12330ej2v0ds 5. system registers (sysreg) 5.1 outline of system registers figure 5-1 shows the location of the system registers on the data memory and their outline. as shown in the figure, the system registers are allocated to addresses 74h through 7fh of all the banks of the data memory. therefore, identical system registers exist at addresses 74h through 7fh of any bank. because the system registers are located on the data memory, they can be manipulated by all data memory manipulation instructions. seven types of system registers are available depending on function. figure 5-1. location and outline of system registers on data memory column address data memory bank0 bank1 bank2 0123456789abcdef 0 1 2 3 4 5 6 7 bank14 bank15 system register address name function 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh address register (ar) controls program memory address window register (wr) transfers data with register file bank register (bank) specifies bank of data memory data memory row address pointer (mp) index register (ix) modifies address of data memory general register pointer (rp) specifies address of general register program status word (psword) controls operation row address ...... remark the pd17717 and 17718 do not have banks 10 through 14.
43 pd17717, 17718, 17719 data sheet u12330ej2v0ds 5.2 system register list figure 5-2 shows the configurations of the system registers. figure 5-2. configuration of system registers address name symbol bit data 74h 75h 76h 77h 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh address register (ar) window register (wr) bank register (bank) data memory row address pointer (mp) index register (ix) general register pointer (rp) program status word (psword) system registers ar3 ar2 ar1 ar0 wr bank ixh mph ixm mpl ixl rph rpl psw b 2 b 1 b 0 b 3 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 m p e 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b c d b 3 b 2 b 1 b 0 c m p c y zi x e (rp) (ix) (mp)
pd17717, 17718, 17719 44 data sheet u12330ej2v0ds 5.3 address register (ar) 5.3.1 configuration of address register figure 5-3 shows the configuration of the address register. as shown in the figure, the address register consists of 16 bits of system register addresses 74h through 77h (ar3 through ar0). figure 5-3. configuration of address register address name symbol bit data 74h ar3 75h ar2 76h ar1 77h ar0 b 3 m s b b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 l s b power-on reset wdt&sp reset ce reset clock stop ?? address register (ar) at reset 0 0 0 retained 0 0 0 retained 0 0 0 retained 0 0 0 retained power-on reset wdt&sp reset ce reset clock stop : reset by reset pin on power application : reset by watchdog timer and stack pointer : ce reset : on execution of clock stop instruction ??
45 pd17717, 17718, 17719 data sheet u12330ej2v0ds 5.3.2 function of address register the address register specifies a program memory address when the table reference instruction (?ovt dbf, @ar?, stack manipulation instruction (?ush ar? ?op ar?, indirect branch instruction (?r @ar?, or indirect subroutine call instruction (?all @ar? is executed. a dedicated instruction (?nc ar? is available that can increment the contents of the address instruction by one. the following paragraphs (1) through (5) describe the operation of the address register when the respective instructions are executed. (1) table reference instruction (?ovt dbf, @ar? when the table reference instruction is executed, the constant data (16 bits) of a program memory address specified by the contents of the address register are read to the data buffer. the constant data that can be specified by the address register is stored to address 0000h to 2fffh in the case of the pd17717, and address 0000h to 3fffh in the case of the pd17718 and 17719. (2) stack manipulation instruction (?ush ar? ?op ar? when the ?ush ar?instruction is executed, the value of the stack pointer is decremented by one, and the contents of the address register (ar) are transferred to an address stack register specified by the stack pointer whose value has been decremented by one. when the ?op ar?instruction is executed, the contents of an address stack register specified by the stack pointer are transferred to the address register, and the value of the stack pointer is incremented by one. (3) indirect branch instruction (?r @ar? when this instruction is executed, the program branches to a program memory address specified by the contents of the address register. the branch address that can be specified by the address register is 0000h to 2fffh in the case of the pd17717, and 0000h to 3fffh in the case of the pd17718 and 17719. (4) indirect subroutine call instruction (?all @ar? the subroutine at a program memory address specified by the contents of the address register can be called. the first address of the subroutine that can be specified by the address register is 0000h to 2fffh in the case of the pd17717, and 0000h to 3fffh in the case of the pd17718 and 17719. (5) address register increment instruction (?nc ar? this instruction increments the contents of the address register by one. 5.3.3 address register and data buffer the address register can transfer data as part of the peripheral hardware via the data buffer. for details, refer to 9. data buffer (dbf) . 5.3.4 cautions on using address register because the address register is configured in 16 bits, it can specify an address up to ffffh. however, the program memory exists at addresses 0000h through 2fffh in the case of the pd17717 and addresses 0000h through 3fffh in the case of the pd17718 and 17719. therefore, the maximum value that can be set to the address register of the pd17717 is address 2fffh. in the case of the pd17718 and 17719, it is address 3fffh.
pd17717, 17718, 17719 46 data sheet u12330ej2v0ds 5.4 window register (wr) 5.4.1 configuration of window register figure 5-4 shows the configuration of the window register. as shown in the figure, the window register consists of 4 bits of system register address 78h (wr). figure 5-4. configuration of window register 5.4.2 function of window register the window register is used to transfer data with the register file (rf) to be described later. data transfer between the window register and register file is manipulated by using dedicated instructions peek wr, rf and poke, rf wr (rf: address of register file). the following paragraphs (1) and (2) describe the operation of the window register when these instructions are executed. for further information, also refer to 8. register file (rf) . (1) ?eek wr, rf?instruction when this instruction is executed, the contents of the register file addressed by rf are transferred to the window register. (2) ?oke rf, wr?instruction when this instruction is executed, the contents of the window register are transferred to the register file addressed by rf . address name symbol bit data clock stop 78h window register (wr) wr undefined retained b 3 m s b b 2 b 1 b 0 l s b power-on reset wdt&sp reset ce reset at reset ?? ??
47 pd17717, 17718, 17719 data sheet u12330ej2v0ds 5.5 bank register (bank) 5.5.1 configuration of bank register figure 5-5 shows the configuration of the bank register. as shown in the figure, the bank register consists of 4 bits of system register address 79h (bank). figure 5-5. configuration of bank register 5.5.2 function of bank register the bank register specifies a bank of the data memory. table 5-1 shows the relationships between the value of the bank register and a bank of the data memory that is specified. because the bank register is one of the system registers, its contents can be rewritten regardless of the bank currently specified. when manipulating a bank register, therefore, the status of the bank at that time is irrelevant. table 5-1. data memory bank specification note do not set banks 10 through 14 in the pd17717 and 17718 because these banks are not provided. caution the area to which the data memory is allocated differs depending on the model. for details, refer to figure 4-2 configuration of data memory. address name symbol bit data clock stop 79h bank register (bank) bank 0 0 0 retained b 3 m s b b 2 b 1 b 0 l s b power-on reset wdt&sp reset ce reset at reset ?? ?? bank register (bank) bank of data memory b 3 b 2 b 1 b 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 bank0 bank1 bank2 bank3 bank4 bank5 bank6 bank7 bank register (bank) bank of data memory b 3 b 2 b 1 b 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 bank8 bank9 bank10 note bank11 note bank12 note bank13 note bank14 note bank15
pd17717, 17718, 17719 48 data sheet u12330ej2v0ds 5.6 index register (ix) and data memory row address pointer (mp: memory pointer) 5.6.1 configuration of index register and data memory row address pointer figure 5-6 shows the configuration of the index register and data memory row address pointer. as shown in the figure, the index register consists of an index register (ix) made up of 11 bits (the low-order 3 bits (ixh) of system register address 7ah, and 7bh and 7ch (ixm, ixl)) and an index enable flag (ixe) at the lowest bit position of 7fh (psw). the data memory row address pointer (memory pointer) consists of a data memory row address pointer (mp) that is made up of 7 bits of the low-order 3 bits of 7ah (mph) and 7bh (mpl), and a data memory row address pointer enable flag (memory pointer enable flag: mpe) at the lowest bit position of 7ah (mph). in other words, the high-order 7 bits of the index register are shared with the data memory row address pointer figure 5-6. configuration of index register and data memory row address pointer address name symbol bit data clock stop 7ah ixh mph 0 0 0 retained 7bh index register (ix) ixm mpl 0 0 0 retained 7ch ixl 0 0 0 retained 7eh 7fh psw memory pointer (mp) b 3 m p e b 2 m s b m s b b 1 b 0 b 3 b 2 b 1 b 0 l s b b 3 b 2 b 1 b 0 l s b b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 i x e 0 0 0 r power-on reset wdt&sp reset ce reset ix program status word (psword) mp at reset r: retained ? ? ? ? ? ? ? ?
49 pd17717, 17718, 17719 data sheet u12330ej2v0ds 5.6.2 functions of index register and data memory row address pointer the index register and data memory row address pointer modify the addresses of the data memory. the following paragraphs (1) and (2) describe their functions. a dedicated instruction ( inc ix ) that increments the value of the index register by one is available. for the details of address modification, refer to 7. alu (arithmetic logic unit) block . (1) index register (ix) when a data memory manipulation instruction is executed, the data memory address is modified by the contents of the index register. this modification, however, is valid only when the ixe flag is set to 1. to modify the address, the bank, row address, and column address of the data memory are ored with the contents of the index register, and the instruction is executed to a data memory address (called real address) specified by the result of this or operation. all data memory manipulation instructions are subject to address modification by the index register. the following instructions, however, are not subject to address modification by the index register. inc ar rorc r inx ix call addr movt dbf, @ar call @ar push ar ret pop ar retsk peek wr,rf reti poke rf,wr ei get dbf,p di put p, dbf stop s br addr halt h br @ar nop (2) data memory row address pointer (mp) when the general register indirect transfer instruction ( mov @r,m or mov m,@r ) is executed, the indirect transfer destination address is modified. this modification, however, is valid only when the mpe flag is set to 1. to modify the address, the bank and row address at the indirect transfer destination are replaced by the contents of the data memory row address pointer. instructions other than the general register indirect transfer instruction are not subject to address modification. (3) index register increment instruction ( inc ix ) this instruction increments the contents of the index register by one. because the index register is configured of 10 bits, its contents are incremented to 000h if the inc ix instruction is executed when the contents of the index register are 3ffh .
pd17717, 17718, 17719 50 data sheet u12330ej2v0ds 5.7 general register pointer (rp) 5.7.1 configuration of general register pointer figure 5-7 shows the configuration of the general register pointer. as shown in the figure, the general register pointer consists of 7 bits including 4 bits of system register address 7dh (rph) and the high-order 3 bits of address 7eh (rpl). figure 5-7. configuration of general register pointer 7dh rph 0 0 0 retained 7eh rpl 0 0 0 retained b 3 m s b b 2 b 1 b 0 b 3 b 2 b 1 l s b b 0 b c d general register pointer (rp) address name symbol bit data clock stop power-on reset wdt&sp reset ce reset at reset ? ? ? ? ? ?
51 pd17717, 17718, 17719 data sheet u12330ej2v0ds 5.7.2 function of general register pointer the general register pointer specifies a general register on the data memory. figure 5-8 shows the addresses of the general registers specified by the general register pointer. as shown in the figure, a bank is specified by the high-order 4 bits (rph: address 7dh) of the general register pointer, and a row address is specified by the low-order 3 bits (rpl: address 7eh). because the valid number of bits of the general register pointer is 7, all the row addresses (0h through 7fh) of all the banks can be specified as general registers. for the details of the operation of the general register, refer to 6. general register (gr) . figure 5-8. address of general register specified by general register pointer remark the pd17717 and 17718 do not have banks 10 through 14. caution the area to which the data memory is allocated differs depending on the model. for details, refer to figure 4-2 configuration of data memory. 5.7.3 cautions on using general register pointer the lowest bit of address 7eh (rpl) of the general register pointer is allocated as the bcd flag of the program status word. when rewriting rpl, therefore, pay attention to the value of the bcd flag. general register pointer (rp) rph rpl b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 specifies row address of each bank bank bank0 bank15 row address 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 specifies bank 0h 1h 2h 3h 4h 5h 6h 7h l s b b c d m s b ? ? ? ? ? ?
pd17717, 17718, 17719 52 data sheet u12330ej2v0ds 5.8 program status word (psword) 5.8.1 configuration of program status word figure 5-9 shows the configuration of the program status word. as shown in the figure, th program status word consists of a total of 5 bits including the lowest bit of system register address 7eh (rpl) and 4 bits of address 7fh (psw). each bit of the program status word has its own function. the 5 bits of the program status word are bcd flag (bcd), compare flag (cmp), carry flag (cy), zero flag (z), and index enable flag (ixe). figure 5-9. configuration of program status word 7eh rpl 0 0 0 retained 7fh psw 0 0 0 retained b 3 b 2 b 1 b 0 b c d b 3 c m p b 2 c y b 1 z b 0 i x e program status word (psword) address name symbol bit data clock stop power-on reset wdt&sp reset ce reset at reset
53 pd17717, 17718, 17719 data sheet u12330ej2v0ds 5.8.2 function of program status word the program status word is a register that sets the conditions under which the alu (arithmetic logic unit) executes an operation or data transfer, or indicates the result of an operation. table 5-2 outlines the function of each flag of the program status word. for details, refer to 7. alu (arithmetic logic unit) block . table 5-2. outline of function of each flag of program status word 5.8.3 cautions on using program status word when an arithmetic operation (addition or subtraction) is executed to the program status word, the result of the arithmetic operation is stored. for example, even if an operation that generates a carry is executed, if the result of the operation is 0000b, 0000b is stored to the psw. program status word (psword) rpl psw b 3 b 2 b 1 b 0 b c d b 3 c m p b 2 c y b 1 z b 0 i x e flag name index enable flag (ixe) zero flag (z) carry flag (cy) compare flag (cmp) bcd flag (bcd) function modifies address of data memory when data memory manipulation instruction is exeuted. 0 : does not modify 1 : modifies indicates result of arithmetic operation is zero. status of this flag differs depending on contents of compare flag. indicates occurrence of carry or borrow as result of execution of addition or subtraction instruction. this flag is reset to 0 if no carry or borrow occurs. it is set to 1 if carry or borrow occurs. this flag is also used as shift bit of rorc r instruction. indicates whether result of arithmetic operation is stored to data memory or general register. 0 : stores result. 1 : does not store result. indicates whether arithmetic operation is performed in decimal or binary. 0 : binary operation 1 : decimla operation (rp)
pd17717, 17718, 17719 54 data sheet u12330ej2v0ds 6. general register (gr) 6.1 outline of general register figure 6-1 outlines the general register. as shown in the figure, the general register is specified in the data memory by the general register pointer. the bank and row address of the general register are specified by the general register pointer. the general register is used to transfer or operate data between data memory addresses. figure 6-1. outline of general register remark the pd17717 and 17718 do not have banks 10 through 14. 6.2 general register the general register consists of 16 nibbles (16 4 bis) of the same row address on the data memory. for the range of the banks and row addresses that can be specified by the general register pointer as a general register, refer to 5.7 general register pointer (rp) . the 16 nibbles of the same row address specified as a general register operate or transfer data with the data memory by a single instruction. in other words, operation or data transfer between data memory addresses can be executed by a single instruction. the general register can be controlled by the data memory manipulation instruction, like the other data memory areas. column address bank2 bank1 bank0 data memory general register transfer, operation general register pointer system register bank15 bank14 row address ??????
55 pd17717, 17718, 17719 data sheet u12330ej2v0ds 6.3 generating address of general register by each instruction the following sections 6.3.1 and 6.3.2 explain how the address of the general register is generated when each instruction is executed. for the details of the operation of each instruction, refer to 7. alu (arithmetic logic unit) block . 6.3.1 add ( add r, m , addc r, m ) , subtract ( sub r, m , subc r, m ) , logical operation ( and r, m , or r, m , xor r, m ), direct transfer ( ld r, m , st m, r ), and rotation ( rorc r ) instructions table 6-1 shows the address of the general register specified by operand r of an instruction. operand r of an instruction specifies only a column address. table 6-1. generating address of general register 6.3.2 indirect transfer ( mov @r, m , mov m, @r ) instruction table 6-2 shows a general register address specified by instruction operand r and an indirect transfer address specified by @r . table 6-2. generating address of general register 6.4 cautions on using general register 6.4.1 row address of general register because the row address of the general register is specified by the general register pointer, the currently specified bank may differ from the bank of the general register. 6.4.2 operation between general register and immediate data no instruction is available that executes an operation between the general register and immediate data. to execute an operation between the general register and immediate data, the general register must be treated as a data memory area. general register address column address row address bank b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 r contents of general register pointer general register address indirect transfer address column address row address bank b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 r contents of general register pointer contents of r same as data memory
pd17717, 17718, 17719 56 data sheet u12330ej2v0ds 7. alu (arithmetic logic unit) block 7.1 outline of alu block figure 7-1 outlines the alu block. as shown in the figure, the alu block consists of an alu, temporary registers a and b, program status word, decimal adjustment circuit, and memory address control circuit. the alu operates on, judges, compares, rotates, and transfers 4-bit data in the data memory. figure 7-1. outline of alu block data bus address control data memory index modification memory pointer temporary register a temporary register b program status word carry/borrow/zero detection/decimal/storage specification alu arithmetic operation logical operation bit judgment comparison rotation transfer decimal adjustment
57 pd17717, 17718, 17719 data sheet u12330ej2v0ds 7.2 configuration and function of each block 7.2.1 alu the alu performs arithmetic operation, logical operation, bit judgment, comparison, rotation, and transfer of 4-bit data according to instructions specified by the program. 7.2.2 temporay registers a and b temporary registers a and b temporarily store 4-bit data. these registers are automatically used when an instruction is executed, and cannot be controlled by program. 7.2.3 program status word the program status word controls the operation of and stores the status of the alu. for further information on the program status word, also refer to 5.8 program status word (psword) . 7.2.4 decimal adjustment circuit the decimal adjustment circuit converts the result of an arithmetic operation into a decimal number if the bcd flag of the program status word is set to 1 during arthmetic operations. 7.2.5 address control circuit the address control circuit specifies an address of the data memory. at this time, address modification by the index register and data memory row address pointer is also controlled. 7.3 alu processing instruction list table 7-1 lists the alu operations when each instruction is executed. table 7-2 shows how data memory addresses are modified by the index register and data memory row address pointer. table 7-3 shows decimal adjustment data when a decimal operation is performed.
pd17717, 17718, 17719 58 data sheet u12330ej2v0ds table 7-1. list of alu processing instruction operations alu instruction difference in operation depending on program status word (psword) address modification function value of value of operation operation of operation of z flag index memory bcd flag cmp flag cy flag pointer add add r, m 0 0 stores result of set if carry or set if result of operation modifies does not m, #n4 binary operation borrow occurs; is 0000b; otherwise, reset modify addc r, m 0 1 does not store result otherwise, reset retains status if result of operation m, #n4 of binary operation is 0000b; otherwise, reset subtract sub r, m 1 0 stores result of set if result of operation m, #n4 decimal operation is 0000b; otherwise, reset subc r, m 1 1 does not store result retains status if result of operation m, #n4 of decimal operation is 0000b; otherwise, reset logical or r, m don t care don t care not affected retains previous retains previous status modifies does not operation m, #n4 (retained) (retained) status modify and r, m m, #n4 xor r, m m, #n4 judge skt m, #n don t care don t care not affected retains previous retains previous status modifies does not skf m, #n (retained) (reset) status modify compare ske m, #n4 don t care don t care not affected retains previous retains previous status modifies does not skne m, #n4 (retained) (retained) status modify skge m, #n4 sklt m, #n4 transfer ld r, m don t care don t care not affected retains previous retains previous status modifies does not st m, r (retained) (retained) status modify mov m, #n4 @r, m modifies m, @r rotate rorc r don t care don t care not affected value of b 0 of retains previous status does not does not (retained) (retained) general register modify modify
59 pd17717, 17718, 17719 data sheet u12330ej2v0ds table 7-2. modification of data memory address and indirect transfer address by index register and data memory row address pointer bank : bank register ix : index register ixe : index enable flag ixh : bits 10 through 8 of index register ixm : bits 7 through 4 of index register ixl : bits 3 through 0 of index register m : data memory address indicated by m r , m c m r : data memory row address (high-order) m c : data memory column address (low-order) mp : data memory row address pointer mpe : memory pointer enable flag r : general register column address rp : general register pointer (x) : contents addressed by x x: direct address such as m and r b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 2 b 1 b 0 b 3 b 2 b 1 b 0 general register address specified by r data memory address specified by m indirect transfer address specified by @r bank row address column address bank row address column address bank row address column address rp r bank m bank m r (r) ditto mp (r) ditto bank m bank m r ix (r) or mp (r) ditto ditto ditto mpe 0 1 0 1 ixe 0 0 1 1 ixh, ixm logical or logical
pd17717, 17718, 17719 60 data sheet u12330ej2v0ds table 7-3. decimal adjustment data operation hexadecimal addition decimal addition operation hexadecimal addition decimal addition result cy operation result cy operation result result cy operation result cy operation result 0 0 0000b 0 0000b 0 0 0000b 0 0000b 1 0 0001b 0 0001b 1 0 0001b 0 0001b 2 0 0010b 0 0010b 2 0 0010b 0 0010b 3 0 0011b 0 0011b 3 0 0011b 0 0011b 4 0 0100b 0 0100b 4 0 0100b 0 0100b 5 0 0101b 0 0101b 5 0 0101b 0 0101b 6 0 0110b 0 0110b 6 0 0110b 0 0110b 7 0 0111b 0 0111b 7 0 0111b 0 0111b 8 0 1000b 0 1000b 8 0 1000b 0 1000b 9 0 1001b 0 1001b 9 0 1001b 0 1001b 10 0 1010b 1 0000b 10 0 1010b 1 1100b 11 0 1011b 1 0001b 11 0 1011b 1 1101b 12 0 1100b 1 0010b 12 0 1100b 1 1110b 13 0 1101b 1 0011b 13 0 1101b 1 1111b 14 0 1110b 1 0100b 14 0 1110b 1 1100b 15 0 1111b 1 0101b 15 0 1111b 1 1101b 16 1 0000b 1 0110b 16 1 0000b 1 1110b 17 1 0001b 1 0111b 15 1 0001b 1 1111b 18 1 0010b 1 1000b 14 1 0010b 1 1100b 19 1 0011b 1 1001b 13 1 0011b 1 1101b 20 1 0100b 1 1110b 12 1 0100b 1 1110b 21 1 0101b 1 1111b 11 1 0101b 1 1111b 22 1 0110b 1 1100b 10 1 0110b 1 0000b 23 1 0111b 1 1101b 9 1 0111b 1 0001b 24 1 1000b 1 1110b 8 1 1000b 1 0010b 25 1 1001b 1 1111b 7 1 1001b 1 0011b 26 1 1010b 1 1100b 6 1 1010b 1 0100b 27 1 1011b 1 1101b 5 1 1011b 1 0101b 28 1 1100b 1 1010b 4 1 1100b 1 0110b 29 1 1101b 1 1011b 3 1 1101b 1 0111b 30 1 1110b 1 1100b 2 1 1110b 1 1000b 31 1 1111b 1 1101b 1 1 1111b 1 1001b remark decimal adjustment is not correctly carried out in the shaded area in the above table.
61 pd17717, 17718, 17719 data sheet u12330ej2v0ds 7.4 cautions on using alu 7.4.1 cautions on execution operation to program status word if an arithmetic operation is executed to the program status word, the result of the operation is stored to the program status word. the cy and z flags in the program status word are usually set or reset by the result of the arithmetic operation. if an arithmetic operation is executed to the program status word itself, the result of the operation is stored to the program status word, and consequently, it cannot be judged whether a carry or borrow occurs or whether the result of the operation is zero. if the cmp flag is set, however, the result of the operation is not stored to the program status word. therefore, the cy and z flags are set or reset normally. 7.4.2 cautions on executing decimal operation the decimal operation can be executed only when the result of the operation falls within the following ranges: (1) result of addition : 0 to 19 in decimal (2) result of subtraction: 0 to 9 or 10 to 1 in decimal if a decimal operation is executed exceeding or falling below the above ranges, the result is a value greater than 1010b (0ah).
pd17717, 17718, 17719 62 data sheet u12330ej2v0ds 8. register file (rf) 8.1 outline of register file figure 8-1 outlines the register file. as shown in the figure, the rgister file consists of the control registers existing on a space different from the data memory, and a portion overlapping the data memory. the control registers set conditions of the peripheral hardware units. the data on the register file can be read or written via window register. figure 8-1. outline of register file control register (on separate space from data memory) (same space as data memory) data manipulation via window register 0 1 2 3 4 5 6 7 system register window register peripheral hardware register file row address
63 pd17717, 17718, 17719 data sheet u12330ej2v0ds 8.2 configuration and function of register file figure 8-2 shows the configuration of the register file and the relationships between the register file and data memory. the register file is assigned addresses in 4-bit units, like the data memory, and consists of a total of 128 nibbles with row addresses 0h through 7fh and column addresses 0h through 0fh. addresses 00h through 3fh are control registers that sets the conditions of the peripheral hardware units. addresses 40h through 7fh overlap the data memory. in other words, addresses 40h through 7fh of the register file are addresses 40h through 7fh of the currently-selected bank of data memory. because addresses 40h through 7fh of the register file overlap the same addresses of the data memory, these addresses of the register file can be manipulated in the same manner as the data memory, except that the addresses of the register file can also be manipulated by using register file manipulation instructions ( peek wr, rf and poke rf, wr ). note, however, that addresses 60h through 6fh of bank15 are assigned port input/output selection registers (for details refer to 8.4 port input/output selection registers ). figure 8-2. configuration of register file and relationship with data memory remark the pd17717 and 17718 do not have banks 10 through 14. column address 0 1 2 3 4 5 6 7 01 234 56789abcdef system registers 0 1 2 3 control registers data memory bank0 bank1 bank2 bank14 register file bank15 port input/output selection registers row address ??????
pd17717, 17718, 17719 64 data sheet u12330ej2v0ds 8.2.1 register file manipulation instructions ( peek wr, rf , poke rf, wr ) data is read from or written to the register file via the window register of the system registers, by using the following instructions. (1) peek wr, rf reads data of the register file addressed by rf to the window register. (2) poke rf, wr writes the data of the window register to the register file addressed by rf . 8.3 control registers figure 8-3 shows the configuration of the control registers. as shown in the figure, the control registers consist of a total of 64 nibbles (64 4 bits) of addresses 00h through 3fh of the register file. of these 64 nibbles, however, only 53 nibbles are actually used. the remaining 11 nibbles are unused registers and prohibited from being written or read. each control register has an attribute of 1 nibble that identifies four types of registers: read/write (r/w), read- only (r), write-only (w), and read-and-reset (r&reset) registers. nothing is changed even if data is written to a read-only (r and r&reset) register. an undefined value is read if a write-only (w) register is read. among the 4-bit data in 1 nibble, the bit fixed to 0 is always 0 when it is read, and is also 0 when it is written. the 11 nibbles of unused registers are undefined when their contents are read, and nothing changes even when they are written. table 8-1 lists the peripheral hardware control functions of the control registers.
65 pd17717, 17718, 17719 data sheet u12330ej2v0ds [memo]
pd17717, 17718, 17719 66 data sheet u12330ej2v0ds figure 8-3. configuration of control registers (1/2) note ( ) indicates an address that is used when the assembler is used. ( ) ( ) s p 3 s p 2 ( ) s p 1 ( ) s p 0 00w d t c k 1 w d t c k 0 w d t r e s 00000 ( ) d b f s p 1 ( ) d b f s p 0 00 i s p r e s a s p r e s c e c n t 3 c e c n t 2 c e c n t 1 c e c n t 0 00m o v t s e l 1 m o v t s e l 0 p l l r f c k 3 p l l r f c k 2 p l l r f c k 1 p l l r f c k 0 000p l l u l 00b e e p 1 s e l b e e p 0 s e l b e e p 1 c k 1 b e e p 1 c k 0 b e e p 0 c k 1 b e e p 0 c k 0 000w d t c y 000b t m 0 c y p l l s c n f 0p l l m d 1 p l l m d 0 000i f c g o s t t i f c m d 1 i f c m d 0 i f c c k 1 i f c c k 0 00i f c s t r t i f c r e s 0a d c c h 2 a d c c h 1 a d c c h 0 0a d c m d a d c s t t a d c c m p 0p w m b i t 0p w m c k 0p w m 2 s e l p w m 1 s e l p w m 0 s e l 00f c g c h 1 f c g c h 0 000 i r q s i o 3 000 i r q s i o 2 000 i r q t m 3 000 i r q t m 2 01 234 5 67 r/w r/w w & reset r r/w r/w r/w read/ write r/w r/w r&reset r/w r/w r&reset r&reset read/ write r/w r r/w w r/w r/w r/w r/w read/ write r r/w r/w r/w r/w read/ write column address row address item name stack pointer watchdog timer clock selection watchdog timer counter reset data buffer stack pointer stack overflow/ underflow reset selection ce reset timer carry counter movt bit selection symbol name pll mode selection pll reference frequency selection pll unlock ff beep/general -purpose port pin function selection beep clock selection watchdog timer/stack pointer reset status detection basic timer 0 carry name fcg channel selection if counter gate status detection if counter mode selection if counter control a/d converter channel selection pwm clock selection pwm/general- purpose port pin function selection a/d converter mode selection symbol name serial interface 3 interrupt request timer 3 interrupt request serial interface 2 interrupt request symbol timer 2 interrupt request 0 1 2 3 (8) note (9) note (a) note (b) note symbol
67 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 8-3. configuration of control register (2/2) s i o 2 c m d t s i o 2 r e l t s i o 2 c l c s i o 2 w r e l s i o 2 w a t 1 s i o 2 w a t 0 0s i o 2 c l d s i o 2 s i c s i o 2 s v a m s i o 2 c m d d s i o 2 r e l d s i o 2 b s y e s i o 2 a c k d s i o 2 a c k e s i o 2 a c k t s i o 2 w u p s i o 2 m d 2 s i o 2 m d 1 s i o 2 m d 0 s i o 2 c s i e s i o 2 c o i s i o 2 t c l 1 s i o 2 t c l 0 s i o 3 c s i e s i o 3 h i z s i o 3 t x e s i o 3 r x e s i o 3 i s r m 0i e g 4 i n t 4 s e l i e g 3 i n t 3 s e l 0i e g 2 i e g 1 i e g 0 00b t m 0 c k 1 b t m 0 c k 0 t m 2 e n t m 2 r e s t m 2 c k 1 t m 2 c k 0 t m 1 e n t m 1 r e s t m 1 c k 1 t m 1 c k 0 t m 0 e n t m 0 r e s t m 0 c k 1 t m 0 c k 0 t m 0 o v f t m 0 g c e g t m 0 g o e g t m 0 m d i p s i o 1 i p s i o 0 i p t m 3 i p t m 2 i p t m 3 i p t m 2 i p 4 i p 3 i p 2 i p 1 i p 0 i p c e t m 3 s e l 0t m 3 e n t m 3 r e s 89abcdef r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w system register interrupt stack pointer serial i/o2 interrupt timing specification register 1 serial i/o2 interrupt timing specification register 2 serial i/o2 sbi register 1 serial i/o2 sbi register 0 serial i/o2 operation mode register 1 serial i/o2 operation mode register 0 basic timer 0 clock selection interrupt edge selection 1 timer 3 control timer 2 counter clock selection timer 1 counter clock selection timer 0 counter clock selection timer 0 mode selection interrupt enable 2 interrupt enable 1 int2 pin interrupt request int0 pin interrupt request ce pin interrupt request 0 s y s r s p 2 s y s r s p 1 serial i/o3 asynchronous mode register 0 interrupt edge selection 2 interrupt enable 3 000 i n t 4 00 i r q 4 i n t 3 00 i r q 3 i n t 2 00 i r q 2 i n t 1 00 i r q 1 i n t 0 00 i r q 0 c e 0c e c n t s t t i r q c e 000i r q t m 1 r/w r/w r/w r/w r/w r/w r/w r i r q t m 0 r / w timer 1 interrupt request timer 0 interrupt request int4 pin interrupt request int3 pin interrupt request int1 pin interrupt request r r / w r/w r r / w r r serial i/o3 operation mode register serial i/o3 asynchronous status register serial i/o3 asynchronous mode register 1 s y s r s p 0 ( ) ( ) ( ) s i o 3 c l s i o 3 s l s i o 3 t c l 1 s i o 3 t c l 0 0s i o 3 p e s i o 3 f e s i o 3 o v e s i o 3 p s 1 s i o 3 p s 0 r/w r r/w
pd17717, 17718, 17719 68 data sheet u12330ej2v0ds table 8-1. peripheral hardware control functions of control registers (1/8) peripheral control register peripheral hardware control function at reset clock hardware name address read/ function set value power- wdt ce stop write symbol on & sp reset 01 reset reset stack stack pointer 01h r/w (sp3) fff retained (sp2) (sp1) (sp0) interrupt stack 08h r 0 fixed to 0 555 retained pointer of (sysrsp2) system register (sysrsp1) (sysrsp0) data buffer 04h r 0 fixed to 0 000 retained stack pointer 0 (dbfsp1) detects nesting level (dbfsp0) of data buffer stack stack overflow/ 05h r/w 0 fixed to 0 3 retained retained retained underflow reset 0 selection ispres selects interrupt stack reset reset valid overflow/underflow reset prohibited (can be set only once following power application) aspres selects address stack overflow/underflow reset (can be set only once following power application) watchdog watchdog timer 02h r/w 0 fixed to 0 3 retained retained retained timer clock selection 0 wdtck1 selects clock of watchdog timer (can be wdtck0 set only once following power application) watchdog timer 03h w & wdtres resets watchdog timer counter invalid reset if written undefined undefined undefined undefined counter reset reset 0 fixed to 0 0 0 wdt&sp reset 16h r & 0 fixed to 0 01 retained retained status detection reset 0 0 wdtcy detects resetting of watchdog no reset reset request timer/stack pointer request b 3 b 2 b 1 b 0 0011 level 0 level 1 level 2 level 3 0101 00 1 1 not 65536 setting 131072 used instruction prohibited instruction 01 0 1
69 pd17717, 17718, 17719 data sheet u12330ej2v0ds table 8-1. peripheral hardware control functions of control registers (2/8) peripheral control register peripheral hardware control function at reset clock hardware name address read/ function set value power- wdt ce stop write symbol on & sp reset 01 reset reset ce ce reset timer 06h r/w cecnt3 sets number of ce reset timer 1 retained retained 1 carry counter cecnt2 carry counts cecnt1 cecnt0 movt bit 07h r/w 0 fixed to 0 000 retained selection 0 movtsel1 sets bit transferred by movt (transferred movtsel0 to dbf1, 0 during 8-bit transfer) serial serial i/o2 0ah r/w sio2clc controls p0a2/scl pin level not affected high impedance 0000 interface interrupt timing (i 2 c bus mode) specification sio2wrel releases wait wait released status releases wait register 1 sio2wat1 controls wait and interrupt 0, 1: issues at rising of 8th clock request issuance (10 and 11 2: issues at rising of 8th clock and waits sio2wat0 are set in i 2 c bus mode) 3: issues at rising of 9th clock and waits serial i/o2 0bh r 0 fixed to 0 0000 interrupt timing sio2cld detects p0a2/scl pin level low level high level specification r/w sio2sic selects interrupt source only on completion on completion of register 0 of transmission transmission or on detection of bus release signal sio2svam selects bit of sio2sva used bits 0-7 bits 1-7 serial i/o2 sbi 0ch r sio2cmdd detects command signal does not detect detects 0000 register 1 sio2reld detects bus release signal does not detect detects r/w sio2cmdt controls trigger output of command automatically clears so2 latch signal cleared after after clearing flag sio2relt controls trigger output of bus release setting flag sets so2 latch signal after setting flag serial i/o2 sbi 0dh r/w sio2bsye controls sync busy signal output disables output enables output 0000 register 0 r sio2ackd detects acknowledge signal does not detect detects r/w sio2acke controls acknowledge signal output disables automatic enables automatic output output sio2ackt controls trigger output of does not output output immediately acknowledge signal acknowledge after set 0: setting prohibited 1: 1 count 2: 2 counts 3: 3 counts 4: 4 counts 5: 5 counts 6: 6 counts 7: 7 counts 8: 8 counts 9: 9 counts a: 10 counts b: 11 counts c: 12 counts d: 13 counts e: 14 counts f: 15 coounts 00 0 1 16-bit high-order low-order transfer 8-bit transfer 8-bit transfer 01 1 0 b 3 b 2 b 1 b 0
pd17717, 17718, 17719 70 data sheet u12330ej2v0ds table 8-1. peripheral hardware control functions of control registers (3/8) peripheral control register peripheral hardware control function at reset clock hardware name address read/ function set value power- wdt ce stop write symbol on & sp reset 01 reset reset serial serial i/o2 0eh r/w sio2wup controls wake-up function disables enables 0000 interface operation mode sio2md2 sets operation mode of serial register 1 sio2md1 interface 2 sio2md0 sets direction of shift clock slave master (external clock) (internal clock) serial i/o2 0fh r/w sio2csie controls operation of serial interface 2 stops operation enables operation 0000 operation mode r sio2coi detects coincidence signal from does not coincide coincide register 0 address comparator r/w sio2tcl1 sets frequency of internal shift sio2tcl0 clock serial i/o3 1ah r/w sio3csie controls operation of serial interface 3 stops operation enables operation 0000 operation mode sio3hiz sets status of so3/p0b1 pin general-purpose serial data output register i/o port sio3tcl1 selects i/o clock of 3-wire sio3tcl0 serial i/o serial i/o3 1bh r 0 fixed to 0 0000 asynchronous sio3pe contents of parity error error does not parity does status register occur not coincide sio3fe contents of framing error error does not stop bit not occur detected sio3ove contents of overrun error error does not data duplication occur serial i/o3 1ch r/w sio3ps1 sets parity bit of uart 0000 asynchronous sio3ps0 mode register 1 sio3cl sets character length of uart 7 bits 8 bits sio3sl sets number of stop bits for 1 2 uart transmission data serial i/o3 1dh r/w sio3txe sets operation of uart 0000 asynchronous sio3rxe mode register 0 sio3isrm sets reception completion enables interrupt disables interrupt interrupt on occurrence of error 0 fixed to 0 0: no parity 1: appends parity during transmission, no parity error during reception 2: odd parity 3: even parity 00 1 1 stops reception transmission transmission/ operation reception 01 0 1 b 3 b 2 b 1 b 0 001 1 93.7 khz 375 khz 281.25 khz 46.875 khz 010 1 0011 external clock 187.5 khz 375 khz 46.875 khz 0101 0: 3-wire serial i/o 1: sbi (sb1 pin) 2: sbi (sb0 pin) 3: 2-wire serial i/o or i 2 c bus
71 pd17717, 17718, 17719 data sheet u12330ej2v0ds table 8-1. peripheral hardware control functions of control registers (4/8) peripheral control register peripheral hardware control function at reset clock hardware name address read/ function set value power- wdt ce stop write symbol on & sp reset 01 reset reset pll pll mode 10h r/w pllscnf sets low-order bits of swallow counter lowest bit is 0 lowest bit is 1 uurr frequency selection 0 fixed to 0 0000 synthesizer pllmd1 sets division mode of pll pllmd0 pll reference 11h r/w pllrfck3 sets reference frequency of pll ffff frequency pllrfck2 selection pllrfck1 pllrfck0 pll unlcok ff 12h r & 0 fixed to 0 undefined undefined retained retained reset 0 0 pllul detects status of unlock ff locked unclocked beep beep/general- 13h r/w 0 fixed to 0 0000 purpose port pin 0 function selection beep1sel selects function of p1d1/beep1 pin general-purpose beep beep0sel selects function of p1d0/beep0 pin i/o port beep clock 14h r/w beep1ck1 sets output frequency of beep1 0000 selection beep1ck0 beep0ck1 sets output frequency of beep0 beep0ck0 timer basic timer 17h r & 0 fixed to 0 0 retained 1 retained 0 carry reset 0 0 btm0cy detects basic timer 0 carry ff ff reset ff set basic timer 0 18h r/w 0 fixed to 0 00 retained retained clock selection 0 btm0ck1 selects clock of basic timer 0 btm0ck0 timer 3 control 28h r/w tm3sel selects timer 3 and d/a converter d/a converter timer 3 0 0 retained 0 0 fixed to 0 tm3en starts or stops timer 3 counter stops starts tm3res resets timer 3 counter not affected reset u: undefined r: retained 0: 1.25 khz 1: 2.5 khz 2: 5 khz 3: 10 khz 4: 6.25 khz 5: 12.5 khz 6: 25 khz 7: 50 khz 8: 3 khz 9: 9 khz a: 18 khz b: setting prohibited c: 1 khz d: 20 khz e: setting prohibited f: pll disabled 0 011 disabled mf vhf hf 0 101 0011 4 khz 3 khz 200 hz 67 hz 0101 0011 1 khz 3 khz 4 khz 6.7 khz 0101 b 3 b 2 b 1 b 0 0011 10 hz 20 hz 50 hz 100 hz 0101
pd17717, 17718, 17719 72 data sheet u12330ej2v0ds table 8-1. peripheral hardware control functions of control registers (5/8) peripheral control register peripheral hardware control function at reset clock hardware name address read/ function set value power- wdt ce stop write symbol on & sp reset 01 reset reset timer timer 2 counter 29h r/w tm2en starts or stops timer 2 counter stops starts 0 0 retained 0 clock selection tm2res resets timer 2 counter not affected reset tm2ck1 sets basic clock of timer tm2ck0 2 counter timer 1 counter 2ah r/w tm1en starts or stops timer 1 counter stops starts 0 0 retained 0 clock selection tm1res resets timer 1 counter not affected reset tm1ck1 sets basic clock of timer tm1ck0 1 counter timer 0 counter 2bh r/w tm0en starts or stops timer 0 counter stops starts 0 0 retained 0 clock selection tm0res resets timer 0 counter not affected reset tm0ck1 sets basic clock of timer tm0ck0 0 counter timer 0 mode 2ch r/w tm0ovf detects timer 0 overflow no overflow overflow 0 0 retained 0 selection tm0gceg sets edge of gate close input rising edge falling edge signal tm0goeg sets edge of gate open input signal tm0md selects modulo counter/gate modulo counter gate counter counter of timer 0 interrupt interrupt edge 1eh r/w ieg4 sets interrupt issuance edge rising edge falling edge 0 0 retained retained selection 1 (int4 pin) int4sel sets interrupt request flag of enables disables p1a3/int4 pin setting of flag setting of flag ieg3 sets interrupt issuance edge rising edge falling edge (int3 pin) int3sel sets interrupt request flag of enables disables p1a2/int3 pin setting of flag setting of flag interrupt edge 1fh r/w 0 fixed to 0 00 retained retained selection 2 ieg2 sets interrupt issuance edge rising edge falling edge (int2 pin) ieg1 sets interrupt issuance edge (int1 pin) ieg0 sets interrupt issuance edge (int0 pin) 0011 100 khz 10 khz 2 khz 1 khz 0101 0011 100 khz 10 khz 2 khz 1 khz 0101 0011 100 khz 10 khz 2 khz 1 khz 0101 b 3 b 2 b 1 b 0
73 pd17717, 17718, 17719 data sheet u12330ej2v0ds table 8-1. peripheral hardware control functions of control registers (6/8) peripheral control register peripheral hardware control function at reset clock hardware name address read/ function set value power- wdt ce stop write symbol on & sp reset 01 reset reset interrupt interrupt enable 1 2dh r/w ipsio3 enables serial interface 3 disables enables 0 0 retained retained interrupt interrupt interrupt ipsio2 enables serial interface 2 interrupt iptm3 enables timer 3 interrupt iptm2 enables timer 2 interrupt interrupt enable 2 2eh r/w iptm1 enables timer 1 interrupt disables enables 0 0 retained retained iptm0 enables timer 0 interrupt interrupt interrupt ip4 enables int4 pin interrupt ip3 enables int3 pin interrupt interrupt enable 3 2fh r/w ip2 enables int2 pin interrupt disables enables 0 0 retained retained ip1 enables int1 pin interrupt interrupt interrupt ip0 enables int0 pin interrupt ipce enables ce pin interrupt serial interface 3 34h r/w 0 fixed to 0 00 retained retained interrupt request 0 0 irqsio3 detects serial interface 3 no interrupt interrupt interrupt request request request serial interface 2 35h r/w 0 fixed to 0 00 retained retained interrupt request 0 0 irqsio2 detects serial interface 2 no interrupt request interrupt request interrupt request timer 3 interrupt 36h r/w 0 fixed to 0 00 retained retained request 0 0 irqtm3 detects timer 3 interrupt request no interrupt request interrupt request timer 2 interrupt 37h r/w 0 fixed to 0 00 retained retained request 0 0 irqtm2 detects timer 2 interrupt request no interrupt request interrupt request timer 1 interrupt 38h r/w 0 fixed to 0 00 retained retained request 0 0 irqtm1 detects timer 1 interrupt request no interrupt request interrupt request b 3 b 2 b 1 b 0
pd17717, 17718, 17719 74 data sheet u12330ej2v0ds table 8-1. peripheral hardware control functions of control registers (7/8) peripheral control register peripheral hardware control function at reset clock hardware name address read/ function set value power- wdt ce stop write symbol on & sp reset 01 reset reset interrupt timer 0 interrupt 39h r/w 0 fixed to 0 00 retained retained request 0 0 irqtm0 detects timer 0 interrupt request no interrupt request interrupt request int4 pin interrupt 3ah r/w int4 detects int4 pin status low level high level uuuu request 0 fixed to 0 00 retained retained 0 irq4 detects int4 pin interrupt request no interrupt request interrupt request int3 pin interrupt 3bh r/w int3 detects int3 pin status low level high level uuuu request 0 fixed to 0 00 retained retained 0 irq3 detects int3 pin interrupt request no interrupt request interrupt request int2 pin interrupt 3ch r/w int2 detects int2 pin status low level high level uuuu request 0 fixed to 0 00 retained retained 0 irq2 detects int2 pin interrupt request no interrupt request interrupt request int1 pin interrupt 3dh r/w int1 detects int1 pin status low level high level uuuu request 0 fixed to 0 00 retained retained 0 irq1 detects int1 pin interrupt request no interrupt request interrupt request int0 pin interrupt 3eh r/w int0 detects int0 pin status low level high level uuuu request 0 fixed to 0 00 retained retained 0 irq0 detects int0 pin interrupt request no interrupt request interrupt request ce pin interrupt 3fh r ce detects ce pin status low level high level uuuu request 0 fixed to 0 0000 cecntstt detects ce reset counter status stops operates r/w irqce detects ce pin interrupt request no interrupt request interrupt request 00rr if fcg channel 20h r/w 0 fixed to 0 0000 counter selection 0 fcgch1 sets pin to be used as fcg fcgch0 if counter gate 21h r 0 fixed to 0 0000 status detection 0 0 ifcgostt detects if counter gate status closed open u: undefined b 3 b 2 b 1 b 0 0011 fcg fcg0 fcg1 setting not used pin pin prohibited 0101
75 pd17717, 17718, 17719 data sheet u12330ej2v0ds table 8-1. peripheral hardware control functions of control registers (8/8) peripheral control register peripheral hardware control function at reset clock hardware name address read/ function set value power- wdt ce stop write symbol on & sp reset 01 reset reset if if counter 22h r/w ifcmd1 sets if counter mode 0000 counter mode selection ifcmd0 ifcck1 sets if counter gate time and ifcck0 fcg count frequency if counter 23h w 0 fixed to 0 0000 control 0 ifcstrt starts or stops if counter nothing affected starts counter ifcres resets if counter data nothing affected starts counter a/d a/d converter 24h r/w 0 fixed to 0 00 retained retained converter channel adcch2 selects pin used for a/d converter selection adcch1 adcch0 a/d converter 25h r/w 0 fixed to 0 0000 mode selection adcmd selects comparison mode of software mode hardware mode retained retained a/d converter r adcstt detects operating status of conversion ends converting 0 0 a/d converter adccmp detects comparison result of v adcref > v adcin v adcref < v adcin 0 retained a/d converter d/a pwm clock 26h r/w 0 fixed to 0 00 retained 0 converter selection pwmbit selects number of bits of pwm 8 bits 9 bits counter 0 fixed to 0 pwmck selects output clock of timer 3 4.4 khz (8)/ 440 hz (8)/ 2.2 khz (9) 220 hz (9) pwm/general- 27h r/w 0 fixed to 0 00 retained 0 purpose port pin pwm2sel selects function of p1b2/pwm2 pin general-purpose d/a converter function selection pwm1sel selects function of p1b1/pwm1 pin output port pwm0sel selects function of p1b0/pwm0 pin 0011 fcg amifc fmifc amifc2 0101 0011 1ms, 4 ms, 8 ms, open, 1 khz 100 khz 900 khz setting prohibited 0101 0: a/d converter not used 1: p0d0/ad0 pin 2: p0d1/ad1pin 3: p0d2/ad2 pin 4: p0d3/ad3 pin 5: p1c2/ad4 pin 6: p1c3/ad5 pin 7: setting prohibited b 3 b 2 b 1 b 0
pd17717, 17718, 17719 76 data sheet u12330ej2v0ds 8.4 port input/output selection registers figure 8-4 shows the configuration of the port input/output selection registers. as shown in this figure, the port input/output select registers consist of a total of 16 nibbles (16 4 bits) at addresses 60h through 6fh of bank 15 of the data memory. table 8-2 lists the control functions of the port input/output selection registers.
77 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 8-4. configuration of port input/output selection registers (1/2) figure 8-4. configuration of port input/output selection registers (2/2) (bank15) column address row address item 6 name symbol read/ write p 0 d p l d 3 p 0 d p l d 2 p 0 d p l d 1 p 0 d p l d 0 p 3 d g i o p 3 c g i o p 3 b g i o p 3 a g i o port 0d pull-down resistor selection group i/o selection 67 45 23 01 r/w r/w p 0 b b i o 3 p 0 b b i o 2 p 0 b b i o 1 p 0 b b i o 0 p 0 a b i o 3 p 0 a b i o 2 p 0 a b i o 1 p 0 a b i o 0 port 0b bit i/o selection port 0a bit i/o selection ef cd ab 89 r/w r/w p 1 d b i o 3 p 1 d b i o 2 p 1 d b i o 1 p 1 d b i o 0 p 0 c b i o 3 p 0 c b i o 2 p 0 c b i o 1 p 0 c b i o 0 port 1d bit i/o selection port 0c bit i/o selection r/w r/w p 2 b b i o 3 p 2 b b i o 2 p 2 b b i o 1 p 2 b b i o 0 0p 2 a b i o 2 p 2 a b i o 1 p 2 a b i o 0 port 2b bit i/o selection port 2a bit i/o selection r/w r/w 0p 2 d b i o 2 p 2 d b i o 1 p 2 d b i o 0 p 2 c b i o 3 p 2 c b i o 2 p 2 c b i o 1 p 2 c b i o 0 port 2d bit i/o selection port 2c bit i/o selection r/w r/w (bank15) column address row address item 6 name symbol read/ write
pd17717, 17718, 17719 78 data sheet u12330ej2v0ds table 8-2. control functions of port input/output selection registers (1/2) peripheral port input/output selection register control function at reset clock hardware name address read/ function set value power- wdt ce stop (bank15) write symbol on & sp reset 01 reset reset input/ port 0d pull- 66h r/w p0dpld3 selects pull-down resistor of p0d3 pin pull-down pull-down 00 retained retained output down resistor p0dpld2 selects pull-down resistor of p0d2 pin resistor used resistor not used port selection p0dpld1 selects pull-down resistor of p0d1 pin p0dpld0 selects pull-down resistor of p0d0 pin group i/o 67h r/w p3dgio selects input/output of port 3d input output 0 0 retained retained selection p3cgio selects input/output of port 3c p3bgio selects input/output of port 3b p3agio selects input/output of port 3a port 2d bit i/o 68h r/w 0 fixed to 0 00 retained retained selection p2dbio2 selects input/output of port p2d2 input output p2dbio1 selects input/output of port p2d1 p2dbio0 selects input/output of port p2d0 port 2c bit i/o 69h r/w p2cbio3 selects input/output of port p2c3 input output 0 0 retained retained selection p2cbio2 selects input/output of port p2c2 p2cbio1 selects input/output of port p2c1 p2cbio0 selects input/output of port p2c0 port 2b bit i/o 6ah r/w p2bbio3 selects input/output of port p2b3 input output 0 0 retained retained selection p2bbio2 selects input/output of port p2b2 p2bbio1 selects input/output of port p2b1 p2bbio0 selects input/output of port p2b0 port 2a bit i/o 6bh r/w 0 fixed to 0 00 retained retained selection p2abio2 selects input/output of port p2a2 input output p2abio1 selects input/output of port p2a1 p2abio0 selects input/output of port p2a0 port 1d bit i/o 6ch r/w p1dbio3 selects input/output of port p1d3 input output 0 0 retained retained selection p1dbio2 selects input/output of port p1d2 p1dbio1 selects input/output of port p1d1 p1dbio0 selects input/output of port p1d0 port 0c bit i/o 6dh r/w p0cbio3 selects input/output of port p0c3 input output 0 0 retained retained selection p0cbio2 selects input/output of port p0c2 p0cbio1 selects input/output of port p0c1 p0cbio0 selects input/output of port p0c0 port 0b bit i/o 6eh r/w p0bbio3 selects input/output of port p0b3 input output 0 0 retained retained selection p0bbio2 selects input/output of port p0b2 p0bbio1 selects input/output of port p0b1 p0bbio0 selects input/output of port p0b0 b 3 b 2 b 1 b 0
79 pd17717, 17718, 17719 data sheet u12330ej2v0ds table 8-2. control functions of port input/output selection registers (2/2) peripheral port input/output selection register control function at reset clock hardware name address read/ function set value power- wdt ce stop (bank15) write symbol on & sp reset 01 reset reset input/ port 0a bit i/o 6fh r/w p0abio3 selects input/output of port p0a3 input output 0 0 retained retained output selection p0abio2 selects input/output of port p0a2 port p0abio1 selects input/output of port p0a1 p0abio0 selects input/output of port p0a0 b 3 b 2 b 1 b 0
pd17717, 17718, 17719 80 data sheet u12330ej2v0ds 8.5 cautions on using register file keep in mind the following points (1) through (3) when using the write-only (w), read-only (r), and unused registers of the control registers (addresses 00h through 3fh of the register file). (1) an undefined value is read if a write-only register is read. (2) nothing is affected even if a read-only register is written. (3) an undefined value is read if an unused register is read. nor is anything affected if this register is written.
81 pd17717, 17718, 17719 data sheet u12330ej2v0ds 9. data buffer (dbf) 9.1 outline of data buffer figure 9-1 outlines the data buffer. the data buffer is located on the data memory and has the following two functions. reads constant data on the program memory (table reference) transfers data with the peripheral hardware units figure 9-1. outline of data buffr data buffer data write (put) data read (get) table reference (movt) peripheral hardware constant data program memory
pd17717, 17718, 17719 82 data sheet u12330ej2v0ds 9.2 data buffer 9.2.1 configuration of data buffer figure 9-2 shows the configuration of the data buffer. as shown in the figure, the data buffer consists of a total of 16 bits of addresses 0ch through 0fh of bank 0 on the data memory. the 16-bit data is configured with bit 3 of address 0ch as the msb and bit 0 of address 0fh as the lsb. because the data buffer is located on the data memory, it can be manipulated by all data memory manipulation instructions. figure 9-2. configuration of data buffer column address 0 1 2 3 4 5 6 7 0123456789abcdef bank0 bank1 bank2 bank14 bank15 system register address bit bit signal data b 3 b 15 b 2 b 14 b 1 b 13 b 0 b 12 dbf3 0ch b 3 b 11 b 2 b 10 b 1 b 9 b 0 b 8 dbf2 0dh b 3 b 7 b 2 b 6 b 1 b 5 b 0 b 4 dbf1 0eh b 3 b 3 b 2 b 2 b 1 b 1 b 0 b 0 dbf0 0fh data memory data buffer remark the pd17717 and 17718 do not have banks 10 through 14. data buffer (dbf) row address data memory ?????? m s b ? ? l s b ? ? data
83 pd17717, 17718, 17719 data sheet u12330ej2v0ds 9.2.2 table reference instruction ( movt dbf, @ar ) this instruction moves the contents of the program memory addressed by the contents of the address register to the data buffer. the number of bits transferred by the table reference instruction can be specified by movt selection register (address 07h) of the control registers. when 8-bit data is transferred, it is read to dbf1 and 0. when the table reference instruction is used, one stack level is used. all the addresses of the program memory can be referenced by the table reference instruction. 9.2.3 peripheral hardware control instructions ( put and get ) the operations of the put and get instructions are as follows: (1) get dbf, p reads the data of a peripheral register addressed by p to the data buffer. (2) put p, dbf sets the data of the data buffer to a peripheral register addressed by p . 9.3 relationships between peripheral hardware and data buffer table 9-1 shows the relationships between the peripheral hardware and the data buffer.
pd17717, 17718, 17719 84 data sheet u12330ej2v0ds table 9-1. relationships between peripheral hardware and data buffer (1/2) peripheral hardware peripheral register transferring data with data buffer name symbol peripheral execution of i/o actual address put/get bit bit instruction a/d converter a/d converter reference adcr 02h put/get 8 8 voltage setting register serial interface serial interface 2 presettable shift register 2 sio2sfr 03h put/get 8 8 serial i/o2 slave address register sio2sva 04h put/get 8 8 serial interface 3 serial i/o3 transmission register sio3txs 05h put 8 8 serial i/o3 reception buffer register sio3rxb get 8 8 timer 0 timer 0 modulo register tm0m 1ah put/get 8 8 timer 0 counter tm0c 1bh get 8 8 timer 1 timer 1 modulo register tm1m 1ch put/get 8 8 timer 1 counter tm1c 1dh get 8 8 timer 2 timer 2 modulo register tm2m 1eh put/get 8 8 timer 2 counter tm2c 1fh get 8 8 address register address register ar 40h put/get 16 16 data buffer stack dbf stack dbfstk 41h put/get 16 16 pll frequency synthesizer note pll data register pllr 42h put/get 16 16 frequency counter ifc data register ifc 43h get 16 16 d/a converter p1b0/pwm0 pin pwm data register 0 pwmr0 44h put/get 16 9 (pwm output) p1b1/pwm1 pin pwm data register 1 pwmr1 45h p1b2/pwm2 pin pwm data register 2 pwmr2 46h put/get 16 9 timer 3 timer 3 modulo register tm3m 8 note the programmable counter of the pll frequency synthesizer is configured of 17 bits, of which the high- order 16 bits indicate the pll data register (pllr) and the low-order bits are allocated to the pllscnf flag (the third bit of address 10h). for details, refer to 17. pll frequency synthesizer .
85 pd17717, 17718, 17719 data sheet u12330ej2v0ds table 9-1. relationships between peripheral hardware and data buffer (2/2) at reset clock function power-on wdt&sp ce stop reset reset reset 000 note 0 note sets compare voltage v adcref of a/d converter undefined undefined undefined undefined sets serial-out data and reads serial-in data undefined undefined undefined undefined sets slave address value of slave device ff ff ff ff sets transmission data in 3-wire serial i/o and uart modes ff ff ff ff stores receive data in 3-wire serial i/o and uart modes ff ff retained ff sets modulo register value of timer 0 00 retained 0 reads count value of timer 0 counter ff ff retained ff sets modulo register value of timer 1 00 retained 0 reads count value of timer 1 counter ff ff retained ff sets modulo register value of timer 2 00 retained 0 reads count value of timer 2 counter 000 retained transfers data with address register undefined undefined retained retained saves data of data buffer undefined undefined retained retained sets division value (n value) of pll 0000 reads count value of frequency counter 1ff 1ff retained 1ff sets duty of output signal of d/a converter sets duty of output signal of d/a converter (multiplexed with modulo register of timer 3) sets modulo register value of timer 3 note value in hardare mode. retained in software mode.
pd17717, 17718, 17719 86 data sheet u12330ej2v0ds 9.4 cautions on using data buffer keep the following points in mind concerning the unused peripheral addresses, write-only peripheral register (put only), and read-only peripheral register (get only) when transferring data with the peripheral hardware via data buffer. an undefined value is read if a write-only register is read. nothing is affected even if a read-only register is written. an undefined value is read if an unused address is read. nor is anything affected if this address is written.
87 pd17717, 17718, 17719 data sheet u12330ej2v0ds 10. data buffer stack 10.1 outline of data buffer stack figure 10-1 outlines the data buffer stack. as shown in the figure, the data buffer stack consists of a data buffer stack pointer and data buffer stack registers. the data buffer stack saves or restores the contents of the data buffer when the put or get instruction is executed. therefore, the contents of the data buffer can be saved by one instruction when an interrupt is accepted. figure 10-1. outline of data buffer stack 10.2 data buffer stack register figure 10-2 shows the configuration of the data buffer stack registers. as shown in the figure, the data buffer stack registers consist of four 16-bit registers. the contents of the data buffer are saved by executing the put instruction, and the saved data is restored by executing the get instruction. the data buffer contents can be successively saved up to 4 levels. data buffer stack pointer dbf data buffer stack registers address specification
pd17717, 17718, 17719 88 data sheet u12330ej2v0ds figure 10-2. configuration of data buffer stack register dbf3 dbf2 dbf1 dbf0 16 bits data buffer transfer data valid data b 15 b 14 b 13 b 12 b 11 b 10 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 data buffer stack register dbfstk 41h get put saves contents of data buffer up to 4 levels bit name symbol address data
89 pd17717, 17718, 17719 data sheet u12330ej2v0ds 10.3 data buffer stack pointer the data buffer stack pointer detects the multiplexing level of the data buffer stack registers. when the put instruction is executed to the data buffer stack, the value of the data buffer stack pointer is incremented by one; when the get instruction is executed, the value of the pointer is decremented by one. the data buffer stack pointer can be only read and cannot be written. the configuration and function of the data buffer stack pointer are illustrated below. name flag symbol b 3 0 b 2 0 b 1 d b f s p 1 b 0 d b f s p 0 address 04h read/write r data buffer stack pointer power-on reset wdt&sp reset ce reset clock stop 0 1 0 1 level 0 level 1 level 2 level 3 detects multiplexing level of data buffer stack 0 0 1 1 retained fixed to 0 000 0 0 0 0 0 at reset
pd17717, 17718, 17719 90 data sheet u12330ej2v0ds 10.4 operation of data buffer stack figure 10-3 shows the operation of the data buffer stack. as shown in the figure, when the put instruction is executed, the contents of the data buffer are transferred to a data buffer stack register specified by the stack pointer, and the stack pointer is incremented by one. when the get instruction is executed, the contents of a data buffer stack register specified by the stack pointer are transferred to the data buffer, and the stack pointer is decremented by one. therefore, note that the value of the stack pointer is set to 1 if data has been written once because its initial value is 0, and that the stack pointer is set to 0 when data has been written four times. note that when writing (put) exceeding four levels, the first data are discarded. figure 10-3. operation of data buffer stack (a) if writing does not exceed level 4 (b) if writing exceeds level 4 undefined undefined undefined undefined v dd a undefined undefined undefined put a b undefined undefined put a b undefined undefined get a b undefined undefined get 0 1 2 3 a undefined undefined undefined put a b undefined undefined put a b c undefined put a b c d e b c d e b c d get e b c d get put put 0 1 2 3
91 pd17717, 17718, 17719 data sheet u12330ej2v0ds 10.5 using data buffer stack a program example is shown below. example to save the contents of the data buffer and address register by using int0 interrupt routine (the contents of the data buffer and address register are not automatically saved when an interrupt occurs). start: br initial ; reset address ; interrupt vector address nop ; si01 nop ; si00 nop ; tm3 nop ; tm2 nop ; tm1 nop ; tm0 nop ; int4 nop ; int3 nop ; int2 nop ; int1 br intint0 ; int0 nop ; down edge of ce intint0: put dbfstk, dbf ; saves contents of dbf to first level of data buffer ; stack (dbfstk) get dbf, ar ; transfers contents of address register (ar) to dbf put dbfstk, dbf ; saves contents of ar to second level of data buffer ; stack processing b ; int0 interrupt processing get dbf, dbfstk ; restores second level of data buffer stack to data buffer, put ar, dbf ; and restores contents of data buffer to address register get dbf, dbfstk ; restores first level of data buffer stack to data buffer ei reti initial: set1 ip0 ei loop: processing a br loop end 10.6 cautions on using data buffer stack the contents of the data buffer stack are not automatically saved when an interrupt is accepted, and therefore, must be saved by software. even when a bank of the data memory other than bank0 is specified, the contents of the data buffer (existing in bank0) can be saved or restored by using the put and get instructions.
pd17717, 17718, 17719 92 data sheet u12330ej2v0ds 11. general-purpose port the general-purpose ports output high-level, low-level, or floating signals to external circuits, and read high- level or low-level signals from external circuits. 11.1 outline of general-purpose port table 11-1 shows the relationships between each port and port register. the general-prupose ports are classified into i/o, input, and output ports. the i/o ports are further subclassified into bit i/o ports that can be set in the input or output mode in 1-bit (1-pin) units, and group i/o ports that can be set in the input or output mode in 4-bit (4-pin) units. the inut or output mode of each i/o port is specified by the port input/output selection registers (addresses 60h through 6fh) of bank15. table 11-1. relationships between port (pin) and port register (1/3) port pin data setting method no. symbol i/o port register (data memory) bank address symbol bit symbol (reserved word) port 0a 63 p0a3 i/o (bit i/o) bank0 70h p0a b 3 p0a3 64 p0a2 b 2 p0a2 65 p0a1 b 1 p0a1 66 p0a0 b 0 p0a0 port 0b 67 p0b3 i/o (bit i/o) 71h p0b b 3 p0b3 68 p0b2 b 2 p0b2 69 p0b1 b 1 p0b1 70 p0b0 b 0 p0b0 port 0c 59 p0c3 i/o (bit i/o) 72h p0c b 3 p0c3 60 p0c2 b 2 p0c2 61 p0c1 b 1 p0c1 62 p0c0 b 0 p0c0 port 0d 22 p0d3 input 73h p0d b 3 p0d3 23 p0d2 b 2 p0d2 24 p0d1 b 1 p0d1 25 p0d0 b 0 p0d0
93 pd17717, 17718, 17719 data sheet u12330ej2v0ds table 11-1. relationships between port (pin) and port register (2/3) port pin data setting method no. symbol i/o port register (data memory) bank address symbol bit symbol (reserved word) port 1a 2 p1a3 input bank1 70h p1a b 3 p1a3 3 p1a2 b 2 p1a2 4 p1a1 b 1 p1a1 5 p1a0 b 0 p1a0 port 1b 17 p1b3 output 71h p1b b 3 p1b3 18 p1b2 b 2 p1b2 19 p1b1 b 1 p1b1 20 p1b0 b 0 p1b0 port 1c 26 p1c3 input 72h p1c b 3 p1c3 27 p1c2 b 2 p1c2 28 p1c1 b 1 p1c1 29 p1c0 b 0 p1c0 port 1d 37 p1d3 i/o (bit i/o) 73h p1d b 3 p1d3 38 p1d2 b 2 p1d2 39 p1d1 b 1 p1d1 40 p1d0 b 0 p1d0 port 2a no pin i/o (bit i/o) bank2 70h p2a b 3 14 p2a2 b 2 p2a2 15 p2a1 b 1 p2a1 16 p2a0 b 0 p2a0 port 2b 43 p2b3 i/o (bit i/o) 71h p2b b 3 p2b3 44 p2b2 b 2 p2b2 45 p2b1 b 1 p2b1 46 p2b0 b 0 p2b0 port 2c 55 p2c3 i/o (bit i/o) 72h p2c b 3 p2c3 56 p2c2 b 2 p2c2 57 p2c1 b 1 p2c1 58 p2c0 b 0 p2c0 port 2d no pin i/o (bit i/o) 73h p2d b 3 71 p2d2 b 2 p2d2 72 p2d1 b 1 p2d1 73 p2d0 b 0 p2d0
pd17717, 17718, 17719 94 data sheet u12330ej2v0ds table 11-1. relationships between port (pin) and port register (3/3) port pin data setting method no. symbol i/o port register (data memory) bank address symbol bit symbol (reserved word) port 3a 6 p3a3 i/o bank3 70h p3a b 3 p3a3 7 p3a2 (group i/o) b 2 p3a2 8 p3a1 b 1 p3a1 9 p3a0 b 0 p3a0 port 3b 10 p3b3 i/o 71h p3b b 3 p3b3 11 p3b2 (group i/o) b 2 p3b2 12 p3b1 b 1 p3b1 13 p3b0 b 0 p3b0 port 3c 47 p3c3 i/o 72h p3c b 3 p3c3 48 p3c2 (group i/o) b 2 p3c2 49 p3c1 b 1 p3c1 50 p3c0 b 0 p3c0 port 3d 51 p3d3 i/o 73h p3d b 3 p3d3 52 p3d2 (group i/o) b 2 p3d2 53 p3d1 b 1 p3d1 54 p3d0 b 0 p3d0 no pin bank4 70h-73h fixed to 0 | bank15 note note pd17717 and 17718 do not have banks 10 through 14.
95 pd17717, 17718, 17719 data sheet u12330ej2v0ds 11.2 general-purpose i/o port (p0a, p0b, p0c, p1d, p2a, p2b, p2c, p2d, p3a, p3b, p3c, p3d) 11.2.1 configuration of i/o port the following paragraphs (1) and (2) show the configuration of the i/o ports. (1) p0a (p0a1, p0a0) p0b (p0b3, p0b2, p0b1, p0b0) p0c (p0c3, p0c2, p0c1, p0c0) p1d (p1d3, p1d2, p1d1, p1d0) p2a (p2a2, p2a1, p2a0) p2b (p2b3, p2b2, p2b1, p2b0) p2c (p2c3, p2c2, p2c1, p2c0) p2d (p2d2) p3a (p3a3, p3a2, p3a1, p3a0) p3b (p3b3, p3b2, p3b1, p3b0) p3c (p3c3, p3c2, p3c1, p3c0) p3d (p3d3, p3d2, p3d1, p3d0) note this is an internal signal that is output when the clock stop instruction is executed, and this circuit is designed not to increase the current consumption due to noise even if it is floated. v dd v dd i/o selection flag output latch 1 0 read instruction port register (1 bit) write instruction ckstop note
pd17717, 17718, 17719 96 data sheet u12330ej2v0ds (2) p0a (p0a3, p0a2) p2d (p2d1, p2d0) note this is an internal signal that is output when the clock stop instruction is executed, and this circuit is designed not to increase the current consumption due to noise even if it is floated. 11.2.2 using i/o port the input or output mode of the i/o ports is set by i/o selection register p0a, p0b, p0c, p1d, p2a, p2b, p2c, p2d, p3a, p3b, p3c, or p3d of the control registers. because p0a, p0b, p0c, p1d, p2a, p2b, p2c, and p2d are bit i/o ports, they can be set in the input or output mode in 1-bit units. p3a, p3b, p3c, and p3d are group i/o ports, and therefore they are set in the input or output mode in 4- bit units. setting the output data of or reading the input data of a port is carried out by executing an instruction that writes data to or reads data from the port. 11.2.3 shows the configuration of the i/o selection register of each port. 11.2.4 and 11.2.5 describe how each port is used as an input or output port. 11.2.6 describes the points to be noted when using the i/o ports. v dd i/o selection flag output latch read instruction port register (1 bit) write instruction ckstop note
97 pd17717, 17718, 17719 data sheet u12330ej2v0ds 11.2.3 i/o port i/o selection register the following i/o selection registers of the i/o ports are available. port 0a bit i/o selection register port 0b bit i/o selection register port 0c bit i/o selection register port 1d bit i/o selection register port 2a bit i/o selection register port 2b bit i/o selection register port 2c bit i/o selection register port 2d bit i/o selection register group i/o selection registers (port 3a, port 3b, port 3c, port 3d) each i/o selection register sets the input or output mode of the corresponding port pin. the following paragraphs (1) through (9) descibe the configuration and functions of the above i/o selection registers.
pd17717, 17718, 17719 98 data sheet u12330ej2v0ds (1) port 0a bit i/o selection register name flag symbol b 3 p 0 a b i o 3 b 2 p 0 a b i o 2 b 1 p 0 a b i o 1 b 0 p 0 a b i o 0 address (bank15) 6fh read/write r/w port 0a bit i/o selection power-on reset wdt&sp reset ce reset clock stop 0 1 sets p0a0 pin in input mode sets p0a0 pin in output mode sets input/output mode of port retained retained sets p0a1 pin in input mode sets p0a1 pin in output mode sets input/output mode of port 0 1 sets p0a2 pin in input mode sets p0a2 pin in output mode sets input/output mode of port 0 1 sets p0a3 pin in input mode sets p0a3 pin in output mode sets input/output mode of port 0 1 0 0 0 0 0 0 0 0 at reset
99 pd17717, 17718, 17719 data sheet u12330ej2v0ds (2) port 0b bit i/o selection register name flag symbol b 3 p 0 b b i o 3 b 2 p 0 b b i o 2 b 1 p 0 b b i o 1 b 0 p 0 b b i o 0 address (bank15) 6eh read/write r/w port 0b bit i/o selection power-on reset wdt&sp reset ce reset clock stop 0 1 sets p0b0 pin in input mode sets p0b0 pin in output mode sets input/output mode of port retained retained sets p0b1 pin in input mode sets p0b1 pin in output mode sets input/output mode of port 0 1 sets p0b2 pin in input mode sets p0b2 pin in output mode sets input/output mode of port 0 1 sets p0b3 pin in input mode sets p0b3 pin in output mode sets input/output mode of port 0 1 0 0 0 0 0 0 0 0 at reset
pd17717, 17718, 17719 100 data sheet u12330ej2v0ds (3) port 0c bit i/o selection register name flag symbol b 3 p 0 c b i o 3 b 2 p 0 c b i o 2 b 1 p 0 c b i o 1 b 0 p 0 c b i o 0 address (bank15) 6dh read/write r/w port 0c bit i/o selection power-on reset wdt&sp reset ce reset clock stop 0 1 sets p0c0 pin in input mode sets p0c0 pin in output mode sets input/output mode of port retained retained sets p0c1 pin in input mode sets p0c1 pin in output mode sets input/output mode of port 0 1 sets p0c2 pin in input mode sets p0c2 pin in output mode sets input/output mode of port 0 1 sets p0c3 pin in input mode sets p0c3 pin in output mode sets input/output mode of port 0 1 0 0 0 0 0 0 0 0 at reset
101 pd17717, 17718, 17719 data sheet u12330ej2v0ds (4) port 1d bit i/o selection register name flag symbol b 3 p 1 d b i o 3 b 2 p 1 d b i o 2 b 1 p 1 d b i o 1 b 0 p 1 d b i o 0 address (bank15) 6ch read/write r/w port 1d bit i/o selection power-on reset wdt&sp reset ce reset clock stop 0 1 sets p1d0 pin in input mode sets p1d0 pin in output mode sets input/output mode of port retained retained sets p1d1 pin in input mode sets p1d1 pin in output mode sets input/output mode of port 0 1 sets p1d2 pin in input mode sets p1d2 pin in output mode sets input/output mode of port 0 1 sets p1d3 pin in input mode sets p1d3 pin in output mode sets input/output mode of port 0 1 0 0 0 0 0 0 0 0 at reset
pd17717, 17718, 17719 102 data sheet u12330ej2v0ds (5) port 2a bit i/o selection register name flag symbol b 3 0 b 2 p 2 a b i o 2 b 1 p 2 a b i o 1 b 0 p 2 a b i o 0 address (bank15) 6bh read/write r/w port 2a bit i/o selection power-on reset wdt&sp reset ce reset clock stop 0 1 sets p2a0 pin in input mode sets p2a0 pin in output mode sets input/output mode of port retained retained sets p2a1 pin in input mode sets p2a1 pin in output mode sets input/output mode of port 0 1 sets p2a2 pin in input mode sets p2a2 pin in output mode sets input/output mode of port 0 1 fixed to 0 0 0 0 0 0 0 0 at reset
103 pd17717, 17718, 17719 data sheet u12330ej2v0ds (6) port 2b bit i/o selection register name flag symbol b 3 p 2 b b i o 3 b 2 p 2 b b i o 2 b 1 p 2 b b i o 1 b 0 p 2 b b i o 0 address (bank15) 6ah read/write r/w port 2b bit i/o selection power-on reset wdt&sp reset ce reset clock stop 0 1 sets p2b0 pin in input mode sets p2b0 pin in output mode sets input/output mode of port retained retained sets p2b1 pin in input mode sets p2b1 pin in output mode sets input/output mode of port 0 1 sets p2b2 pin in input mode sets p2b2 pin in output mode sets input/output mode of port 0 1 sets p2b3 pin in input mode sets p2b3 pin in output mode sets input/output mode of port 0 1 0 0 0 0 0 0 0 0 at reset
pd17717, 17718, 17719 104 data sheet u12330ej2v0ds (7) port 2c bit i/o selection register name flag symbol b 3 p 2 c b i o 3 b 2 p 2 c b i o 2 b 1 p 2 c b i o 1 b 0 p 2 c b i o 0 address (bank15) 69h read/write r/w port 2c bit i/o selection power-on reset wdt&sp reset ce reset clock stop 0 1 sets p2c0 pin in input mode sets p2c0 pin in output mode sets input/output mode of port retained retained sets p2c1 pin in input mode sets p2c1 pin in output mode sets input/output mode of port 0 1 sets p2c2 pin in input mode sets p2c2 pin in output mode sets input/output mode of port 0 1 sets p2c3 pin in input mode sets p2c3 pin in output mode sets input/output mode of port 0 1 0 0 0 0 0 0 0 0 at reset
105 pd17717, 17718, 17719 data sheet u12330ej2v0ds (8) port 2d bit i/o selection register name flag symbol b 3 0 b 2 p 2 d b i o 2 b 1 p 2 d b i o 1 b 0 p 2 d b i o 0 address (bank15) 68h read/write r/w port 2d bit i/o selection power-on reset wdt&sp reset ce reset clock stop 0 1 sets p2d0 pin in input mode sets p2d0 pin in output mode sets input/output mode of port retained retained sets p2d1 pin in input mode sets p2d1 pin in output mode sets input/output mode of port 0 1 sets p2d2 pin in input mode sets p2d2 pin in output mode sets input/output mode of port 0 1 fixed to 0 0 0 0 0 0 0 0 at reset
pd17717, 17718, 17719 106 data sheet u12330ej2v0ds (9) group i/o selection register (ports 3a, 3b, 3c, 3d) name flag symbol b 3 p 3 d g i o b 2 p 3 c g i o b 1 p 3 b g i o b 0 p 3 a g i o address (bank15) 67h read/write r/w group i/o selection power-on reset wdt&sp reset ce reset clock stop 0 1 sets p3a0 through p3a3 pins in input mode sets p3a0 through p3a3 pins in output mode sets input/output mode of port retained retained sets p3b0 through p3b3 pins in input mode sets p3b0 through p3b3 pins in output mode sets input/output mode of port 0 1 sets p3c0 through p3c3 pins in input mode sets p3c0 through p3c3 pins in output mode sets input/output mode of port 0 1 sets p3d0 through p3d3 pins in input mode sets p3d0 through p3d3 pins in output mode sets input/output mode of port 0 1 0 0 0 0 0 0 0 0 at reset
107 pd17717, 17718, 17719 data sheet u12330ej2v0ds 11.2.4 when using i/o port as input port the port pin to be set in the input mode is selected by the i/o selection register corresponding to the port. ports p0a, p0b, p0c, p1d, p2a, p2b, p2c, and p2d can be set in the input or output mode in 1-bit units. p3a, p3b, p3c, and p3d can be set in the input or output mode in 4-bit units. the pin set in the input mode is floated (hi-z) and waits for input of an external signal. the input data is read by executing a read instruction (such as skt) to the port register corresponding to the port pin. 1 is read from the port register when a high level is input to the corresponding port pin; when a low level is input to the port pin, 0 is read from the register. when a write instruction (such as mov) is executed to the port register corresponding to the pin set in the input mode, the contents of the output latch are rewritten. 11.2.5 when using i/o port as output port the port pin to be set in the output mode is selected by the i/o selection register corresponding to the port. ports p0a, p0b, p0c, p1d, p2a, p2b, p2c, and p2d can be set in the input or output mode in 1-bit units. p3a, p3b, p3c, and p3d can be set in the input or output mode in 4-bit units. the pin set in the output mode outputs the contents of the output latch. the output data is set by executing a write instruction (such as mov) to the port register corresponding to the port pin. write 1 to the port register to output a high level to the port pin; write 0 to output a low level. the port pin can be also floated (hi-z) if it is set in the input mode. if a read instruction (such as skt) is executed to the port register corresponding to a port pin set in the output mode, the contents of the output latch are read. note, however, that the contents of the output latch of the p0a3 and p0a2 pins may differ from the read contents because the status of these pins are read as are (refer to 11.2.6 ). 11.2.6 cautions on using i/o port (p0a3 and p0a2 pins) when using the p0a3 and p0a2 pins in the output mode, the contents of the output latch may be rewritten as shown in the example below. example to set the p0a3 and p0a2 pins in the output mode bank15 initflg p0abi03, p0abi02, not p0abi01, not p0abi00 ; sets p0a3 and p0a2 pins in output mode initflg p0a3, p0a2, not p0a1, not p0a0 ; outputs high level to p0a3 and p0a2 pins ; <1> clr1 p0a3 ; outputs low level to p0a3 pin macro extend and .mf.p0a3 shr 4, #.df.(not p0a3 and 0fh) if the p0a2 pin is externally made low when the instruction in the above example <1> is executed, the contents of the output latch of the p0a2 pin are rewritten to 0 by the clr1 instruction. in other words, if an instruction that reads the contents of port register p0a is executed while the p0a3 or p0a2 pin is set in the output mode, the contents of the output latch are rewritten to the pin level at that time, regardless of the previous status.
pd17717, 17718, 17719 108 data sheet u12330ej2v0ds 11.2.7 status of i/o port at reset (1) at power-on reset all the i/o ports are set in the input mode. the contents of the output latch are reset to 0 . (2) at wdt&sp reset all the i/o ports are set in the input mode. the contents of the output latch are reset to 0 . (3) at ce reset the setting of the input or output mode is retained. the contents of the output latch are also retained. (4) on execution of clock stop instruction the setting of the input or output mode is retained. the contents of the output latch are also retained. (5) in halt status the previous status is retained.
109 pd17717, 17718, 17719 data sheet u12330ej2v0ds 11.3 general-purpose input port (p0d, p1a, p1c) 11.3.1 configuration of input port the following paragraphs (1) and (2) show the configuration of the input port. (1) p0d (p0d3, p0d2, p0d1, p0d0) note this is an internal signal output on execution of the clock stop instruction, and its circuit is designed not to increase the current consumption due to noise even if the pin is floated. (2) p1a (p1a3, p1a2, p1a1, p1a0) p1c (p1c3, p1c2, p1c1, p1c0) note this is an internal signal output on execution of the clock stop instruction, and its circuit is designed not to increase the current consumption due to noise even if the pin is floated (except p1a3, p1a2, and p1a0). v dd to frequency counter or a/d converter write instruction read instruction port register (1 bit) ckstop note v dd write instruction read instruction port register (1 bit) ckstop note p0dpld flag high-on resistance input latch to a/d converter
pd17717, 17718, 17719 110 data sheet u12330ej2v0ds 11.3.2 using input port the input data is read by executing a read instruction (such as skt) to the port register corresponding to the port pin. 1 is read from the port register when a high level is input to the corresponding port pin; when a low level is input to the port pin, 0 is read from the register. nothing is affected even if a write instruction (such as mov) is executed to the port register. p0d has a pull-down resistor that can be connected or disconnected by software in 1-bit units. the pull-down resistor is connected when 0 is written to the corresponding bit of the port 0d pull-down resistor selection register. when 1 is written to the corresponding bit of this register, the pull-down resistor is disconnected. 11.3.3 port 0d pull-down resistor selection register the port 0d pull-down resistor selection register specifies whether a pull-down resistor is connected to p0d3 through p0d0 pins. the configuration and function of this register are illustrated below. port 0d pull-down resistor selection register name flag symbol b 3 p 0 d p l d 3 b 2 p 0 d p l d 2 b 1 p 0 d p l d 1 b 0 p 0 d p l d 0 address (bank15) 66h read/write r/w port 0d pull-down resistor selection power-on reset wdt&sp reset ce reset clock stop 0 1 connects pull-down resistor to p0d0 pin disconnects pull-down resistor from p0d0 pin selects pull-down resistor of p0d0 pin retained retained connects pull-down resistor to p0d1 pin disconnects pull-down resistor from p0d1 pin selects pull-down resistor of p0d1 pin 0 1 connects pull-down resistor to p0d2 pin disconnects pull-down resistor from p0d2 pin selects pull-down resistor of p0d2 pin 0 1 connects pull-down resistor to p0d3 pin disconnects pull-down resistor from p0d3 pin selects pull-down resistor of p0d3 pin 0 1 0 0 0 0 0 0 0 0 at reset
111 pd17717, 17718, 17719 data sheet u12330ej2v0ds 11.3.4 status of input port at reset (1) at power-on reset all the input ports are set in the input mode. all the pull-down resistors of p0d are connected. (2) at wdt&sp reset all the input ports are set in the input mode. all the pull-down resistors of p0d are connected. (3) at ce reset the input ports are set in the input mode. the pull-down resistors of p0d retain the previous status. (4) on execution of clock stop instruction the input ports are set in the input mode. the pull-down resistors of p0d retain the previous status. (5) in halt status the previous status is retained.
pd17717, 17718, 17719 112 data sheet u12330ej2v0ds 11.4 general-purpose output port (p1b) 11.4.1 configuration of output port the configuration of the output port is shown below. (1) p1b (p1b3, p1b2, p1b1, p1b0) 11.4.2 using output port the output port outputs the contents of the output latch to each pin. the output data is set by executing a write instruction (such as mov) to the port register corresponding to the port pin. write 1 to the port register to output a high level to the port pin; write 0 to output a low level. however, because p1b is an n-ch open-drain output port, it is floated when it outputs a high level. therefore, an external pull-up resistor must be connected to this port. if a read instruction (such as skt) is executed to the port register, the contents of the output latch are read. 11.4.3 status of output port at reset (1) at power-on reset the contents of the output latch are output. the contents of the output latch are reset to 0 . (2) at wdt&sp reset the contents of the output latch are output. the contents of the output latch are reset to 0 . (3) at ce reset the contents of the output latch are output. the contents of the output latch are retained. (4) on execution of clock stop instruction the contents of the output latch are output. the contents of the output latch are retained. (5) in halt status the contents of the output latch are output. the contents of the output latch are retained. output latch read instruction port register (1 bit) write instruction
113 pd17717, 17718, 17719 data sheet u12330ej2v0ds 12. interrupt 12.1 outline of interrupt block figure 12-1 outlines the interrupt block. as shown in the figure, the interrupt block temporarily stops the currently executed program and branches execution to a vector address in response to an interrupt request output by a peripheral hardware unit. the interrupt block consists of an interrupt request servicing block corresponding to each peripheral hardware unit, interrupt enable flip-flop that enables all interrupts, stack pointer that is controlled when an interrupt is accepted, address stack registers , program counter , and interrupt stack . the interrupt control block of each peripheral hardware unit consists of an interrupt request flag (irq ) that detects the corresponding interrupt request, interrupt enable flag (ip ) that enables the interrupt, and vector address generator (vag) that specifies a vector address when the interrupt is accepted. the pd17719 has the following 12 types of maskable interrupts. ce pin falling edge interrupt int0 through int4 interrupts timer 0 through timer 3 interrupts serial interface 2 and serial interface 3 interrupts when an interrupt is accepted, execution branches to a predetermined address, and the interrupt is serviced.
pd17717, 17718, 17719 114 data sheet u12330ej2v0ds figure 12-1. outline of interrupt block serial interface 3 ipsio3 flag serial interface 2 ipsio2 flag timer 3 iptm3 flag timer 2 iptm2 flag timer 1 iptm1 flag timer 0 iptm0 flag int4 pin ip4 flag int3 pin ip3 flag int2 pin ip2 flag int1 pin ip1 flag int0 pin ip0 flag ce pin falling ipce flag program counter address stack registers stack pointer interrupt stack pointer interrupt control block interrupt enable flip-flop di, ei instruction irqsio3 flag irqsio2 flag irqtm3 flag irqtm2 flag irqtm1 flag irqtm0 flag irqint4 flag irqint3 flag irqint2 flag irqint1 flag irqint0 flag irqce flag vector address generator 01h vector address generator 02h vector address generator 03h vector address generator 04h vector address generator 05h vector address generator 06h vector address generator 07h vector address generator 08h vector address generator 09h vector address generator 0ah vector address generator 0bh vector address generator 0ch system registers
115 pd17717, 17718, 17719 data sheet u12330ej2v0ds 12.2 interrupt control block an interrupt control block is provided for each peripheral hardware unit. this block detects issuance of an interrupt request, enables the interrupt, and generates a vector address when the interrupt is accepted. 12.2.1 configuration and function of interrupt request flag (irq ) each interrupt request flag is set to 1 when an interrupt request is issued by the corresponding peripheral hardware unit, and is reset to 0 when the interrupt is accepted. writing the interrupt request flag to 1 via a window register is equivalent to issuance of the interrupt request. by detecting the interrupt request flag when an interrupt is not enabled, issuance status of each interrupt request can be detected. once the interrupt request flag has been set, it is not reset until the corresponding interrupt is accepted, or until 0 is written to the flag via a window register. even if two or more interrupt requests are issued at the same time, the interrupt request flag corresponding to the interrupt that has not been accepted is not reset. figures 12-2 through 12-13 show the configuration and function of the respective interrupt request registers. figure 12-2. configuration of serial interface 3 interrupt request register name flag symbol b 3 0 b 2 0 b 1 0 b 0 i r q s i o 3 address 34h read/write r/w serial interface 3 interrupt request power-on reset wdt&sp reset ce reset clock stop 0 1 interrupt request not issued interrupt request issued indicates interrupt request issuance status of serial interface 3 fixed to 0 0 0 r r 0 0 0 r: retained at reset
pd17717, 17718, 17719 116 data sheet u12330ej2v0ds figure 12-3. configuration of serial interface 2 interrupt request register figure 12-4. configuration of timer 3 interrupt request register name flag symbol b 3 0 b 2 0 b 1 0 b 0 i r q t m 3 address 36h read/write r/w timer 3 interrupt request power-on reset wdt&sp reset ce reset clock stop 0 1 interrupt request not issued interrupt request issued indicates interrupt request issuance status of timer 3 fixed to 0 0 0 r r 0 0 0 r: retained at reset name flag symbol b 3 0 b 2 0 b 1 0 b 0 i r q s i o 2 address 35h read/write r/w serial interface 2 interrupt request power-on reset wdt&sp reset ce reset clock stop 0 1 interrupt request not issued interrupt request issued indicates interrupt request issuance status of serial interface 2 fixed to 0 0 0 r r 0 0 0 r: retained at reset
117 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 12-5. configuration of timer 2 interrupt request register figure 12-6. configuration of timer 1 interrupt request register name flag symbol b 3 0 b 2 0 b 1 0 b 0 i r q t m 1 address 38h read/write r/w timer 1 interrupt request power-on reset wdt&sp reset ce reset clock stop 0 1 interrupt request not issued interrupt request issued indicates interrupt request issuance status of timer 1 fixed to 0 0 0 r r 0 0 0 r: retained at reset name flag symbol b 3 0 b 2 0 b 1 0 b 0 i r q t m 2 address 37h read/write r/w timer 2 interrupt request power-on reset wdt&sp reset ce reset clock stop 0 1 interrupt request not issued interrupt request issued indicates interrupt request issuance status of timer 2 fixed to 0 0 0 r r 0 0 0 r: retained at reset
pd17717, 17718, 17719 118 data sheet u12330ej2v0ds figure 12-7. configuration of timer 0 interrupt request register name flag symbol b 3 0 b 2 0 b 1 0 b 0 i r q t m 0 address 39h read/write r/w timer 0 interrupt request power-on reset wdt&sp reset ce reset clock stop 0 1 interrupt request not issued interrupt request issued indicates interrupt request issuance status of timer 0 fixed to 0 0 0 r r 0 0 0 r: retained at reset
119 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 12-8. configuration of int4 pin interrupt request register name flag symbol b 3 i n t 4 b 2 0 b 1 0 b 0 i r q 4 address 3ah read/write r/w int4 pin interrupt request power-on reset wdt&sp reset ce reset clock stop 0 1 interrupt request not issued interrupt request issued indicates interrupt request issuance status of int4 pin fixed to 0 low level is input high level is input detects status of int4 pin 0 1 0 0 r r 0 0 u u u u u: undefined, r : retained at reset
pd17717, 17718, 17719 120 data sheet u12330ej2v0ds figure 12-9. configuration of int3 pin interrupt request register name flag symbol b 3 i n t 3 b 2 0 b 1 0 b 0 i r q 3 address 3bh read/write r/w int3 pin interrupt request power-on reset wdt&sp reset ce reset clock stop 0 1 interrupt request not issued interrupt request issued indicates interrupt request issuance status of int3 pin fixed to 0 low level is input high level is input detects status of int3 pin 0 1 0 0 r r 0 0 u u u u u: undefined, r : retained at reset
121 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 12-10. configuration of int2 pin interrupt request register name flag symbol b 3 i n t 2 b 2 0 b 1 0 b 0 i r q 2 address 3ch read/write r/w int2 pin interrupt request power-on reset wdt&sp reset ce reset clock stop 0 1 interrupt request not issued interrupt request issued indicates interrupt request issuance status of int2 pin fixed to 0 low level is input high level is input detects status of int2 pin 0 1 0 0 r r 0 0 u u u u u: undefined, r : retained at reset
pd17717, 17718, 17719 122 data sheet u12330ej2v0ds figure 12-11. configuration of int1 pin interrupt request register name flag symbol b 3 i n t 1 b 2 0 b 1 0 b 0 i r q 1 address 3dh read/write r/w int1 pin interrupt request power-on reset wdt&sp reset ce reset clock stop 0 1 interrupt request not issued interrupt request issued indicates interrupt request issuance status of int1 pin fixed to 0 low level is input high level is input detects status of int1 pin 0 1 0 0 r r 0 0 u u u u u: undefined, r: retained at reset
123 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 12-12. configuration of int0 pin interrupt request register name flag symbol b 3 i n t 0 b 2 0 b 1 0 b 0 i r q 0 address 3eh read/write r/w int0 pin interrupt request power-on reset wdt&sp reset ce reset clock stop 0 1 interrupt request not issued interrupt request issued indicates interrupt request issuance status of int0 pin fixed to 0 low level is input high level is input detects status of int0 pin 0 1 0 0 r r 0 0 u u u u u: undefined, r: retained at reset
pd17717, 17718, 17719 124 data sheet u12330ej2v0ds figure 12-13. configuration of ce pin interrupt request register name flag symbol b 3 c e b 2 0 b 1 c e c n t s t t b 0 i r q c e address 3fh read/write r/w ce pin interrupt request power-on reset wdt&sp reset ce reset clock stop 0 1 u u u u 00 0 0 0 0 0 r r 0 1 interrupt request not issued interrupt request issued indicates interrupt request issuance status of ce pin stops operates detects status of ce reset counter fixed to 0 low level is input high level is input detects status of ce pin 0 1 u : undefined, r : retained at reset
125 pd17717, 17718, 17719 data sheet u12330ej2v0ds 12.2.2 function and configuration of interrupt request flag (ip ) each interrupt request flag enables the interrupt of the corresponding peripheral hardware unit. in order for an interrupt to be accepted, all the following conditions must be satisfied. the interrupt must be enabled by the corresponding interrupt request flag. the interrupt request must be issued by the corresponding interrupt request flag. the ei instruction (which enables all interrupts) must be executed. the interrupt enable flags are located on the interrupt enable register on the register file. figures 12-14 through 12-16 show the configuration and function of each interrupt enable register. figure 12-14. configuration of interrupt enable register 1 name flag symbol b 3 i p s i o 3 b 2 i p s i o 2 b 1 i p t m 3 b 0 i p t m 2 address 2dh read/write r/w interrupt enable 1 power-on reset wdt&sp reset ce reset clock stop at reset 0 1 0 0 0 0 0 0 0 0 0 1 disables enables enables or disables timer 2 interrupt disables enables enables or disables timer 3 interrupt disables enables enables or disables serial interface 2 interrupt disables enables enables or disables serial interface 3 interrupt 0 1 0 1 retained retained
pd17717, 17718, 17719 126 data sheet u12330ej2v0ds figure 12-15. configuration of interrupt enable register 2 name flag symbol b 3 i p t m 1 b 2 i p t m 0 b 1 i p 4 b 0 i p 3 address 2eh read/write r/w interrupt enable 2 power-on reset wdt&sp reset ce reset at reset 0 1 0 0 0 0 0 0 0 0 0 1 disables enables enables or disables int3 pin interrupt enables or disables int4 pin interrupt enables or disables timer 0 interrupt enables or disables timer 1 interrupt 0 1 0 1 retained retained clock stop disables enables disables enables disables enables
127 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 12-16. configuration of interrupt enable register 3 name flag symbol b 3 i p 2 b 2 i p 1 b 1 i p 0 b 0 i p c e address 2fh read/write r/w interrupt enable 3 at reset 0 1 0 0 0 0 0 0 0 0 0 1 enables or disables ce pin interrupt enables or disables int0 pin interrupt enables or disables int1 pin interrupt enables or disables int2 pin interrupt 0 1 0 1 power-on reset wdt&sp reset ce reset disables enables retained retained clock stop disables enables disables enables disables enables
pd17717, 17718, 17719 128 data sheet u12330ej2v0ds 12.2.3 vector address generator (vag) the vector address generator generates a branch address (vector address) of the program memory corresponding to an interrupt source that has been accepted from the corresponding peripheral hardware. table 12-1 shows the vector addresses of the respective interrupt sources. table 12-1. interrupt sources and vector addresses interrupt source vector address falling edge of ce pin 00ch int0 pin 00bh int1 pin 00ah int2 pin 009h int3 pin 008h int4 pin 007h timer 0 006h timer 1 005h timer 2 004h timer 3 003h serial interface 2 002h serial interface 3 001h
129 pd17717, 17718, 17719 data sheet u12330ej2v0ds 12.3 interrupt stack register 12.3.1 configuration and function of interrupt stack register figure 12-17 shows the configuration of the interrupt stack register. the interrupt stack register saves the contents of the following system registers (except the address register (ar)) when an interrupt is accepted. window register (wr) bank register (bank) index register (ix) general pointer (rp) program status word (psword) when an interrupt is accepted and the contents of the above system registers are saved to the interrupt stack, the contents of the above system registers, except the window register, are reset to 0 . the interrupt stack can save the contents of the above system registers at up to four levels. therefore, interrupts can be nested up to four levels. the contents of the interrupt stack register are restored to the system registers when the interrupt return (reti) instruction is executed. the contents of the interrupt stack register are undefined at power-on reset. the previous contents are retained at ce reset and on execution of the clock stop instruction. figure 12-17. configuration of interrupt stack register window stack wrsk b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 b 3 b 2 b 1 b 0 bank stack banksk index stack h ixhsk index stack m ixhsk index stack l ixhsk pointer stack h rphsk pointer stack l rplsk status stack pswsk bit undefined interrupt stack register (intsk) name address 0h 1h 2h 3h 4h 5h intsk1 intsk2 intsk3 intsk4 interrupt stack pointer of system register bit b 2 b 3 b 0 b 1 s y s r s p 2 0s y s r s p 0 s y s r s p 1 undefined
pd17717, 17718, 17719 130 data sheet u12330ej2v0ds 12.3.2 interrupt stack pointer of system register the interrupt stack pointer of the system register detects the nesting level of interrupts. the interrupt stack pointer can be only read and cannot be written. the configuration and function of the interrupt stack pointer are illustrated below. name flag symbol b 3 0 address 08h read/write r interrupt stack pointer of system registers 01 1 1 0 0 0 1 1 1 use prohibited 4 levels (intsk1) 3 levels (intsk2) 2 levels (intsk3) 1 level (intsk4) 0 level detects level of interrupt stack of system registers fixed to 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 1 power-on reset wdt&sp reset ce reset retained at reset clock stop b 2 s y s r s p 2 b 1 s y s r s p 1 b 0 s y s r s p 0 ( ) ( ) ( )
131 pd17717, 17718, 17719 data sheet u12330ej2v0ds 12.3.3 interrupt stack operation figure 12-8 shows the operation of the interrupt stack. when nested interrupts exceeding four levels are accepted, since the contents saved first are discarded they therefore must be saved by the program. figure 12-18. operation of interrupt stack (1/2) (a) where interrupt nesting level is 4 or less undefined undefined undefined undefined main undefined undefined undefined undefined main undefined undefined undefined a main undefined undefined undefined a main undefined undefined b a main undefined undefined main routine interrupt a interrupt b reti reti
pd17717, 17718, 17719 132 data sheet u12330ej2v0ds figure 12-18. operation of interrupt stack (2/2) (b) where interrupt nesting level is 5 or more caution the system is reset when an interrupt of level 5 is accepted. however, the ispres flag, which resets the non-maskable interrupt if the interrupt stack overflows or underflows, must be set to ?? this flag is ??after system reset, and can then be written only once. undefined undefined main main undefined undefined undefined a a main undefined undefined b main routine interrupt level 1 interrupt level 2 c b a main d d c b a e interrupt d interrupt e interrupt level 4 interrupt level 5 s y stem reset interrupt a interrupt c
133 pd17717, 17718, 17719 data sheet u12330ej2v0ds 12.4 stack pointer, address stack registers, and program counter the address stack registers save a return address when execution returns from an interrupt routine. the stack pointer specifies the address of an address stack register. when an interrupt is accepted, the value of the stack pointer is decremented by one, and the value of the program counter at that time is saved to an address stack register specified by the stack pointer. next, the interrupt routine is executed. when the interrupt return (reti) instruction is executed after that, the contents of an address stack register specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. for further information, also refer to 3. address stack (ask) . 12.5 interrupt enable flip-flop (inte) the interrupt enable flip-flop enables or disables the 12 types of maskable interrupts. when this flip-flop is set, all the interrupts are enabled. when it is reset, all the interrupts are disabled. this flip-flop is set or reset by dedicated instructions ei (to set) and di (to reset). the ei instruction sets this flip-flop when the instruction next to ei is executed, and the di instruction resets the flip-flop while it is being executed. when an interrupt is accepted, this flip-flop is automatically reset. this flip-flop is also reset at power-on reset, at a reset by the reset pin, at a watchdog timer, overflow or underflow of the stack, and at ce reset. the flip-flop retains the previous status on execution of the clock stop instruction.
pd17717, 17718, 17719 134 data sheet u12330ej2v0ds 12.6 accepting interrupt 12.6.1 accepting interrupt and priority the following operations are performed before an interrupt is accepted. (1) each peripheral hardware unit outputs an interrupt request signal to the corresponding interrupt request block if a given interrupt condition (for example, input of the falling signal to the int0 pin) is satisfied. (2) when each interrupt request block accepts an interrupt request signal from the corresponding peripheral hardware unit, it sets the corresponding interrupt request flag (for example, irq0 flag if it is the int0 pin that has issued the interrupt request) to 1 . (3) the interrupt enable flag corresponding to each interrupt request flag (for example, ip0 flag if the interrupt request flag is irq0) is set to 1 when each interrupt request flag is set to 1 , and each interrupt request block outputs 1 . (4) the signal output by the interrupt request block is ored with the output of the interrupt enable flip-flop, and an interrupt accept signal is output. this interrupt enable flip-flop is set to 1 by the ei instruction, and reset to 0 by the di instruction. if 1 is output by each interrupt request processing block while the interrupt enable flip-flop is set to 1 , the interrupt is accepted. as shown in figure 12-1, the output of the interrupt enable flip-flop is input to each interrupt request block via an and circuit when an interrupt is accepted. the signal input to each interrupt request block causes the interrupt request flag corresponding to each interrupt request flag to be reset to 0 and the vector address corresponding to each interrupt to be output. if the interrupt request block outputs 1 at this time, the interrupt accept signal is not transferred to the next stage. if two or more interrupt requests are issued at the same time, therefore, the interrupts are accepted according to the priority shown in table 12-2. unless the interrupt request enable flag is set to 1 , the corresponding interrupt is not accepted. therefore, by resetting the interrupt enable flag to 0 , the interrupt with a high hardware priority can be disabled. table 12-2. interrupt priority interrupt source priority falling edge of ce pin 1 int0 pin 2 int1 pin 3 int2 pin 4 int3 pin 5 int4 pin 6 timer 0 7 timer 1 8 timer 2 9 timer 3 10 serial interface 2 11 serial interface 3 12
135 pd17717, 17718, 17719 data sheet u12330ej2v0ds 12.6.2 timing chart when interrupt is accepted the timing charts in figure 12-19 illustrate the operations performed when an interrupt or interrupts are accepted. figure 12-19 (1) is the timing chart when one interrupt is accepted. (a) in (1) is the timing chart where the interrupt request flag is set to 1 after all the others, and (b) is the timing chart where the interrupt enable flag is set to 1 after all the others. in either case, the interrupt is accepted when the interrupt request flag, interrupt enable-flip flop, and interrupt enable flag all have been set to 1 . if the flag or flip-flop that has been set last is set in the first instruction cycle of the movt dbf, @ar instruction or by an instruction that satisfies a given skip condition, the interrupt is accepted in the second instruction cycle of the movt dbf, @ar instruction or after the instruction that is skipped (this instruction is treated as nop) has been executed. the interrupt enable flip-flop is set in the instruction cycle next to that in which the ei instruction is executed. therefore, the interrupt is accepted after the instruction next to the ei instruction has been executed even when the interrupt request flag is set in the execution cycle of the ei instruction. (2) in figure 12-19 is the timing chart where two or more interrupts are used. when two or more interrupts are used, the interrupts are accepted according to the hardware priority if all the interrupt enable flags are set. however, the hardware priority can be changed by setting the interrupt enable flags by the program. instruction cycle shown in figure 12-19 is a special cycle in which the interrupt request flag is reset, a vector address is specified, and the contents of the program counter are saved after an interrupt has been accepted. it takes 1.78 s, which is equivalent to one instruction execution time, to be completed. for details, refer to 12.7 operation after interrupt has been accepted .
pd17717, 17718, 17719 136 data sheet u12330ej2v0ds figure 12-19. timing charts when interrupt is accepted (1/3) (1) when one interrupt (e.g., rising of int0 pin) is used (a) if there is no interrupt mask time by the interrupt flag (ip ) <1> if a normal instruction which is not ?ovt?or an instruction that satisfies a skip condition is executed when interrupt is accepted <2> if ?ovt?or an instruction that satisfies a skip condition is executed when interrupt is accepted instruction ei mov wr, #0010b poke intpm3, wr normal instruction interrupt cycle inte int0 pin irq0 flag ip0 flag 1 instruction cycle 1.78 s interrupt enable period int0 pin interrupt accepted int0 pin interrupt service instruction ei mov wr, #0010b poke intpm3, wr movt dbf, @ar or skip instruction interrupt cycle inte 1.78 s interrupt enable period int0 pin interrupt accepted int0 pin interrupt service int0 pin irq0 flag ip0 flag 1 instruction cycle
137 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 12-19. timing charts when interrupt is accepted (2/3) (b) if interrupt is kept pending by the interrupt enable flag (2) if two or more interrupts (e.g., int0 pin and int1 pin) are used (a) hardware priority instruction ei mov wr, #0010b poke intpm3, wr interrupt cycle inte int0 pin irq0 flag ip0 flag int0 pin interrupt pending period int0 pin interrupt accepted int0 pin interrupt service instruction ei mov wr, #0110b poke intpm3, wr interrupt cycle inte int0 pin irq0 flag int1 pin int0 pin interrupt pending period int0 pin interrupt accepted int0 pin interrupt service ei interrupt cycle irq1 flag ip0 flag ip1 flag int1 pin interrupt pending period int1 pin interrupt service int1 pin interrupt accepted
pd17717, 17718, 17719 138 data sheet u12330ej2v0ds figure 12-19. timing charts when interrupt is accepted (3/3) (b) software priority instruction ei mov wr, #0100b poke intpm3, wr interrupt cycle inte int0 pin irq0 flag int1 pin int1 pin interrupt pending period int1 pin interrupt accepted int1 pin interrupt service ei interrupt cycle irq1 flag ip0 flag ip1 flag int0 pin interrupt pending period int0 pin interrupt service int0 pin interrupt accepted mov wr, #0110b poke intpm3, wr
139 pd17717, 17718, 17719 data sheet u12330ej2v0ds 12.7 operations after interrupt has been accepted when an interrupt is accepted, the following operations are sequentially performed automatically. (1) the interrupt enable flip-flop and the interrupt request flag corresponding to the accepted interrupt request are reset to 0 . as a result, the other interrupts are disabled. (2) the contents of the stack pointer are decremented by one. (3) the contents of the program counter are saved to an address stack register specified by the stack pointer. at this time, the contents of the program counter are the program memory address after the address at which the interrupt has been accepted. for example, if a branch instruction is executed when the interrupt has been accepted, the contents of the program counter are the branch destination address. if a subroutine call instruction is executed, the contents of the program counter are the call destination address. if the skip condition of a skip instruction is satisfied, the next instruction is executed as nop and then the interrupt is accepted. consequently, the contents of the program counter are the address after that of the instruction that is skipped. (4) the contents of the system registers (except the address register) are saved to the interrupt stack. (5) the contents of the vector address generator corresponding to the interrupt that has been accepted are transferred to the program counter. in other words, execution branches to the interrupt routine. the operations (1) through (5) above require the time of one special instruction cycle (1.78 s) in which normal instruction execution is not performed. this instruction cycle is called an interrupt cycle . in other words, the time of one instruction cycle (1.78 s) is required after an interrupt has been accepted until execution branches to the corresponding vector address. 12.8 returning from interrupt routine the interrupt return (reti) instruction is used to return from an interrupt routine to the processing during which an interrupt was accepted. when the reti instruction is executed, the following operations are sequentially performed automatically. (1) the contents of an address stack register specified by the stack pointer are restored to the program counter. (2) the contents of the interrupt stack are restored to the system registers. (3) the contents of the stack pointer are incremented by one. the operations (1) through (3) above require one instruction cycle (1.78 s) in which the reti instruction is executed. the only difference between the reti instruction and the ret and retsk instructions, which are subroutine return instructions, is the restoration of the bank register and index register in step (2) above.
pd17717, 17718, 17719 140 data sheet u12330ej2v0ds 12.9 external interrupts (ce and int0 through int4 pins) 12.9.1 outline of external interrupts figure 19-20 outlines the external interrupts. as shown in the figure, external interrupt requests are issued at the rising or falling edges of signals input to the int0 through int4 pins, and at the falling edge of the ce pin. whether an interrupt request is issued at the rising or falling edge of an int pin is independently specified by the program. the int0 through int4 and ce pins are schmitt trigger input pins to prevent malfunctioning due to noise. these pins do not accept a pulse input of less than 100 ns. figure 12-20. outline of external interrupts int0 int0 flag ieg0 flag edge detection block schmitt trigger irq0 flag int1 int1 flag ieg1 flag edge detection block schmitt trigger irq1 flag int2 int2 flag ieg2 flag edge detection block schmitt trigger irq2 flag int3 int3 flag ieg3 flag edge detection block schmitt trigger irq3 flag int4 int4 flag ieg4 flag edge detection block schmitt trigger irq4 flag ce ce flag edge detection block schmitt trigger irqce flag int4sel int3sel interrupt control block
141 pd17717, 17718, 17719 data sheet u12330ej2v0ds 12.9.2 edge detection block the edge detection block specifies the valid edge (rising or falling edge) of an input signal that issues the interrupt request of int0 to int4 pins, by using an interrupt edge selection register. figure 12-21 shows the configuration and function of the interrupt edge selection register. figure 12-21. configuration of interrupt edge selection register (1/2) caution the external input delays about 100 ns. name flag symbol b 3 i e g 4 b 2 i n t 4 s e l b 1 i e g 3 b 0 i n t 3 s e l address 1eh read/write r/w interrupt edge selection 1 power-on reset wdt&sp reset ce reset clock stop at resat 0 1 0 0 0 0 0 0 0 0 0 1 interrupt pin (edge detection cricuit operates) general-purpose port pin (edge detection cricuit stops) selects function of p1a2/int3 pin rising edge falling edge selects input edge to issue interrupt request (int3 pin) interrupt pin (edge detection cricuit operates) general-purpose port pin (edge detection cricuit stops) selects function of p1a3/int4 pin rising edge falling edge selects input edge to issue interrupt request (int4 pin) 0 1 0 1 retained retained
pd17717, 17718, 17719 142 data sheet u12330ej2v0ds figure 12-21. configuration of interrupt edge selection register (2/2) caution the external input is delayed about 100 ns. note that an interrupt request signal may be issued at the time when the interrupt request issuance edge is switched by the interrupt edge selection flags (ieg0 through ieg4). as indicated in the table 12-3, for example, if the ieg0 flag is set to 1 (falling edge), the high level is input from the int0 pin and the ieg0 flag is reset to 0 , the edge detection circuit judges that the rising edge is input and an interrupt request is issued. name flag symbol b 3 0 b 2 i e g 2 b 1 i e g 1 b 0 i e g 0 address 1fh read/write r/w interrupt edge selection 2 power-on reset wdt&sp reset ce reset clock stop at resat 00 0 0 0 0 0 0 1 rising edge falling edge selects input edge to issue interrupt request (int0 pin) rising edge falling edge selects input edge to issue interrupt request (int1 pin) rising edge falling edge selects input edge to issue interrupt request (int2 pin) fixed to 0 0 1 0 1 retained retained
143 pd17717, 17718, 17719 data sheet u12330ej2v0ds table 12-3. issuance of interrupt request by changing ieg flag changes in ieg0 through ieg4 flags status of int0 through int4 pins issuance of interrupt request status of interrupt request flag 1 0 low level not issued retains previous status (falling) (rising) high level issued set to 1 0 1 low level issued set to 1 (rising) (falling) high level not issued retains previous status 12.9.3 interrupt control block the signal levels that are input to the int0 through int4 pins can be detected by using the int0 through int4 flags. because these flags are reset independently of interrupts, when the interrupt function is not used the int0 through int2 pins can be used as a 3-bit input port, and p1a2/int3 and p1a3/int4 pins can be used as a 2- bit general-purpose input port. if the interrupts are not enabled, these ports can be used as general-purpose port pins whose rising or falling edge can be detected by reading the corresponding interrupt request flags. at this time, however, the interrupt request flags are not automatically reset and must be reset by the program. for further information, also refer to 12.2.1 configuration and function of interrupt request flag (irq ) . 12.10 internal interrupts the following six internal interrupts are available. timer 0 timer 1 timer 2 timer 3 serial interface 2 serial interface 3 12.10.1 timer 0, timer 1, timer 2, and timer 3 interrupts interrupt requests are issued at fixed intervals. for details, refer to 13. timer . 12.10.2 serial interface 2 and serial interface 3 interrupts interrupt requests can be issued at the end of a serial output or serial input operation. for details, refer to 16. serial interface .
pd17717, 17718, 17719 144 data sheet u12330ej2v0ds 13. timers timers are used to manage the program execution time. 13.1 outline of timers figure 13-1 outlines the timers. the following five timers are available. basic timer 0 timer 0 timer 1 timer 2 timer 3 basic timer 0 detects the status of a flip-flop that is set at fixed time intervals in software. timers 0 through 3 are modulo timers and can use interrupts. basic timer 0 can also be used to detect a power failure. timer 3 is multiplexed with the d/a converter. the clock of each timer is created by dividing the system clock (4.5 mhz). figure 13-1. outline of timers (1/2) (1) basic timer 0 (2) timer 0 (3) timer 1 clock selection 4.5 mhz btm0cy flag flip-flop clock selection 4.5 mhz gate control tm0g start/stop 8-bit counter interrupt control coincidence detection overflow modulo register clock selection 4.5 mhz start/stop 8-bit counter interrupt control coincidence detection modulo register
145 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 13-1. outline of timers (2/2) (4) timer 2 (5) timer 3 clock selection 4.5 mhz start/stop 8-bit counter interrupt control coincidence detection modulo register clock divider 4.5 mhz start/stop interrupt control coincidence detection multiplexed whih d/a converter modulo register 8-bit counter or 9-bit counter
pd17717, 17718, 17719 146 data sheet u12330ej2v0ds 13.2 basic timer 0 13.2.1 outline of basic timer 0 figure 13-2 outlines basic timer 0. basic timer 0 is used as a timer by detecting in software the btm0cy flag that is set at fixed intervals (100, 50, 20, or 10 ms). if the btm0cy flag is read first after power-on reset, 0 is always read. after that, the flag is set to 1 at fixed intervals. if the ce pin goes high, ce reset is effected in synchronization with the timing at which the btm0cy flag is set next. therefore, a power failure can be detected by reading the content of the btm0cy flag at system reset (power- on reset or ce reset). for the details of power failure detection, refer to 21. reset . figure 13-2. outline of basic timer 0 remarks 1. btm0ck1 and btm0ck0 (bits 1 and 0 of basic timer 0 clock selection register: refer to figure 13-3 ) set the time intervals at which the btm0cy flag is set. 2. btm0cy (bit 0 of basic timer 0 carry register: refer to figure 13-4 ) detects the status of the flip-flop. divider clock selection block 4.5 mhz btm0cy flag selector btm0ck0 flag btm0ck1 flag flip-flop
147 pd17717, 17718, 17719 data sheet u12330ej2v0ds 13.2.2 clock selection block the clock selection block divides the system clock (4.5 mhz) and sets the time interval at which the btm0cy flag is to be set, by using the btm0ck0 and btm0ck1 flags. figure 13-3 shows the configuration of the basic timer 0 clock selection register. figure 13-3. configuration of basic timer 0 clock selection register name flag symbol b 3 0 b 2 0 b 1 b t m 0 c k 1 b 0 b t m 0 c k 0 address 18h read/write r/w basic timer 0 clock selection power-on reset wdt&sp reset ce reset clock stop at reset 0 1 0 1 0 0 10 hz (100 ms) 20 hz (50 ms) 50 hz (20 ms) 100 hz (10 ms) fixed to 0 sets time interval at which btm0cy flag is set 00 0 0 1 1 0 0 retained retained
pd17717, 17718, 17719 148 data sheet u12330ej2v0ds 13.2.3 flip-flop and btm0cy flag the flip-flop is set at fixed intervals and its status is detected by the btm0cy flag of the basic timer 0 carry register. when the btm0cy flag is read, it is reset to 0 (read & reset). the btm0cy flag is 0 at power-on reset, and is 1 at ce reset and on execution of the clock stop instruction. therefore, this flag can be used to detect a power failure. the btm0cy flag is not set after power application until an instruction that reads it is executed. once the read instruction has been executed, the flag is set at fixed intervals. figure 13-4 shows the configuration of the basic timer 0 carry register. figure 13-4. configuration of basic timer 0 carry register name flag symbol b 3 0 b 2 0 b 1 0 b 0 b t m 0 c y address 17h read/write r & reset basic timer 0 carry power-on reset wdt&sp reset ce reset r: retained clock stop at reset 0 1 0 r 1 r flip-flop is not set flip-flop is set fixed to 0 detects status of flip-flop 000
149 pd17717, 17718, 17719 data sheet u12330ej2v0ds 13.2.4 example of using basic timer 0 an example of a program using basic timer 0 is shown below. this program executes processing a every 1 second. example clr2 btm0ck1, btm0ck0 ; sets btm0cy flag setting pulse to 10 hz (100 ms) mov m1, #0 loop: skt1 btm0cy ; branches to next if btm0cy flag is 0 br next add m1, #1 ; adds 1 to m1 ske m1, #0ah ; executes processing a if m1 is 10 (1 second has elapsed) br next mov m1, #0 processing a next: processing b ; executes processing b and branches to loop br loop
pd17717, 17718, 17719 150 data sheet u12330ej2v0ds 13.2.5 errors of basic timer 0 errors of basic timer 0 include an error due to the detection time of the btm0cy flag, and an error that occurs when the time interval at which the btm0cy flag is to be set is changed. the following paragraphs (1) and (2) describe each error. (1) error due to detection time of btm0cy flag the time to detect the btm0cy flag must be shorter than the time at which the btm0cy flag is set (refer to 13.2.6 notes on using basic timer 0 ). where the time interval at which the btm0cy flag is detected is t check and the time interval at which the flag is set is t set (100, 50, 20, or 10 ms), t check and t set must relate as follows. t check < t set at this time, the error of the timer when the btm0cy flag is detected is as follows, as shown in figure 13-5. 0 < error < t set figure 13-5. error of basic timer 0 due to detection time of btm0cy flag as shown in figure 13-5, the timer is updated because btm0cy flag is 1 when it is detected in step <2>. when the flag is detected next in step <3>, it is 0 . therefore, the timer is not updated until the flag is detected again in <4>. this means that the timer is extended by the time of t check3 . h l btm0cy flag setting pulse t set t check1 skt1 btm0cy <1> skt1 btm0cy <2> skt1 btm0cy <3> skt1 btm0cy <4> t check2 t check3 1 0 btm0cy flag
151 pd17717, 17718, 17719 data sheet u12330ej2v0ds (2) error when time interval to set btm0cy flag is changed the btm0ck1 and btm0ck0 flags set the time of the btm0cy flag. as described in 13.2.2, four types of timer time-setting pulses can be selected: 10 hz, 20 hz, 50 hz, and 100 hz. at this time, these four pulses operate independently. if the timer time-setting pulse is changed by using the btm0ck1 and btm0ck0 flags, an error occurs as described in the example below. example ; <1> intiflg not btm0ck1, not btm0ck0 ; sets btm0cy flag setting pulse to 10 hz (100 ms) processing a ; <2> initflg btm0ck1, not btm0ck0 ; sets btm0cy flag setting pulse to 50 hz (20 ms) processing a ; <3> initflg not btm0ck1, not btm0ck0 ; sets btm0cy flag setting pulse to 10 hz (100 ms) at this time, the btm0cy flag setting pulse is changed as shown in figure 13-6. figure 13-6. changing btm0cy flag setting pulse as shown in figure 13-6, if the btm0cy flag setting time is changed and the new pulse falls, the btm0cy flag retains the previous status (<2> in the figure). if the new pulse rises, however, the btm0cy flag is set to 1 (<3> in the figure). although changing the pulse setting between 10 hz (100 ms) and 50 hz (20 ms) is described in this example, the same applies to changing the pulse in respect to 20 hz (50 ms) and 100 hz (10 ms). h l internal pulse 10 hz internal pulse 50 hz h l btm0cy flag 1 0 btm0cy flag setting pulse h l skt1 btm0cy <2> <3> <1>
pd17717, 17718, 17719 152 data sheet u12330ej2v0ds therefore, as shown in figure 13-7, the error of the time until the btm0cy flag is first set after the btm0cy flag setting time has been changed is as follows: t set < error < t check t set : new setting time of btm0cy flag t check : time to detect btm0cy flag phase differences are provided among the internal pules of 10, 20, 50, and 100 hz. because these phase differences are shorter than the newly set pulse time, they are included in the above error. figure 13-7. timer error when btm0cy flag setting time is changed from a to b h l h l h l h l t set skt1 btm0cy intrinsic timer time actual timer time time changed internal pulse a internal pulse b btm0cy flag setting pulse btm0cy flag t set t check actual timer time intrinsic timer time time changed an error of t check occurs if the timer time is changed immediately after btm0cy flag has been detected because the flag is then reset once. an error of -t set occurs if btm0cy flag is detected immediately after the timer time has been changed because the flag then becomes 1 .
153 pd17717, 17718, 17719 data sheet u12330ej2v0ds 13.2.6 cautions on using basic timer 0 (1) btm0cy flag detection time interval keep the time to detect the btm0cy flag shorter than the time at which the btm0cy flag is set. this is because, if the time of processing b is longer than the time interval at which the btm0cy flag is set as shown in figure 13-8, setting of the btm0cy flag is overlooked. figure 13-8. btm0cy flag detection and btm0cy flag (2) timer updating processing time and btm0cy flag detection time interval as described in (1) above, time interval t set at which the btm0cy flag is detected must be shorter than the time for which to set the btm0cy flag. at this time, even if the time interval at which the btm0cy flag is detected is short, if the updating processing time of the timer is long the processing of the timer may not be executed normally at ce reset. therefore, the following condition must be satisfied. t check + t timer < t set t check : time to detect btm0cy flag t timer : timer updating processing time t set : time to set btm0cy flag an example is given below. h btm0cy flag setting pulse btm0cy flag l skt1 btm0cy skt1 btm0cy processing a processing b skt1 btm0cy t set <1> <2> <3> <4> <5> 1 0 because execution time of processing b takes too long after detection of btm0cy flag that has been set to 1 in <2>, btm0cy flag that is set to 1 in <3> cannot be detected.
pd17717, 17718, 17719 154 data sheet u12330ej2v0ds example example of timer updating processing and btm0cy flag detection time interval start: clr2 btm0ck1, btm0ck0 ; sets btm0cy flag setting pulse to 10 hz (100 ms) btimer: ; <1> skt1 btm0cy ; updates timer if btm0cy flag is 1 br aaa timer updating br btimer aaa: processing a br btimer the timing chart of the above program is shown below. (3) compensating basic timer 0 carry at ce reset next, an example of compensating the timer at ce reset is described below. as shown in the example below, the timer must be compensated at ce reset if the btm0cy flag is used for power failure detection and if the btm0cy flag is used for a watch timer . the btm0cy flag is reset (to 0) first on power application (power-on reset), and is disabled from being set until it is read once by the peek instruction. if the ce pin goes high, ce reset is effected in synchronization with the rising edge of the btm0cy flag setting pulse. at this time, the btm0cy flag is set (to 1) and the timer is started. by detecting the status of the btm0cy flag at system reset (power-on reset or ce reset), therefore, it can be identified whether a power-on reset or ce reset has been effected (power failure detection). that is, power-on reset has been effected if the flag is 0 , and ce reset has been effected if it is 1 . at this time, the watch timer must continue operating even if ce reset has been effected. however, because the btm0cy flag is reset to 0 when it is read to detect a power failure, the set status (1) of the btm0cy flag is overlooked once. if the delay function of ce reset is used, the value set to the ce reset timer carry counter (control register address 06h) is overlooked. consequently, the watch timer must be updated if ce reset is identified by means of power failure detection. for the details of power failure detection, refer to 21. reset . t set h ce pin btm0cy detection interval t check timer updating processing t timer btm0cy flag btm0cy flag setting pulse l h l 1 <1> skt1 btm0cy <2> skt1 btm0cy ce reset 0 if this timer updating processing time is too long, ce reset is effected during processing.
155 pd17717, 17718, 17719 data sheet u12330ej2v0ds example example of compensating timer at ce reset (to detect power failure and update watch timer using btm0cy flag) start: ; program address 0000h processing a ; <1> skt1 btm0cy ; embedded macro ; tests btm0cy flag br initial ; if 0 , branches to initial (power failure detection) backup: ; <2> 100-ms watch updating ; compensates watch timer because of backup (ce reset) ; initial value 1 is stored as ce reset timer carry ; counter value loop: ; <3> processing b : while performing processing b, skf1 btm0cy ; tests btm0cy flag and updates watch timer br backup br loop initial: clr2 btm0ck1, btm0ck0 ; embedded macro ; because power failure (power-on reset) occurs, ; sets setting time of btm0cy flag to 100 ms, and ; executes processing c processing c br loop figure 13-9 shows the timing chart of the above program.
pd17717, 17718, 17719 156 data sheet u12330ej2v0ds figure 13-9. timing chart as shown in figure 13-9, the program is started from address 0000h because the internal 10-hz pulse rises when supply voltage v dd is first applied. when the btm0cy flag is detected at point a, it is judged that the btm0cy flag is reset (to 0) and that a power failure (power-on reset) has occurred because the power has just been applied. therefore, processing c is executed, and the btm0cy flag setting pulse is set to 100 ms. because the content of the btm0cy flag is read once at point a, the btm0cy flag will be set to 1 every 100 ms. next, even if the ce pin goes low at point b and high at point c, the program counts up the watch timer while executing processing b , unless the clock stop instruction is executed. at point c, because the ce pin goes high, ce reset is effected at point d at which the btm0cy flag setting pulse rises next time, and the program is started from address 0000h. when the btm0cy flag is detected at point e at this time, it is set to 1. therefore, this is judged to be a back up (ce reset). as is evident from the above figure, unless the watch is updated by 100 ms at point e, the watch is delayed by 100 ms each time ce reset is effected. if processing a takes longer than 100 ms when a power failure is detected at point e, the setting of the btm0cy flag is overlooked two times. therefore, processing a must be completed within 100 ms. the above description also applies when the btm0cy flag setting pulse is set to 50, 20, or 10 ms. therefore, the btm0cy flag must be detected for power failure detection within the btm0cy flag setting time after the program has been started from address 0000h. a power-on reset start from address 0 ce reset start from address 0 application of supply voltage btm0cy flag detected c 5 v v dd ce btm0cy flag setting pulse (10 hz) btm0cy flag program processing program instruction 0 v h l h l 1 0 bb b b b bbb bb <3> watch up <3> watch up <3> watch up <3> <3> <1> watch up <3> <3> <3> <3> <3> <1> a updates watch timer because setting of btm0cy flag (to 1) is detected point a point b point c point d point e
157 pd17717, 17718, 17719 data sheet u12330ej2v0ds (4) if btm0cy flag is detected at the same time as ce reset as described in (3) above, ce reset is effected as soon as the btm0cy flag is set to 1. if the instruction that reads the btm0cy flag happens to be executed at the same time as ce reset at this time, the btm0cy flag reading instruction takes precedence. therefore, if the next setting the btm0cy flag (rising of btm0cy flag setting pulse) after the ce pin has gone high coincides with execution of the btm0cy flag reading instruction, ce reset is effected at the next timing at which the btm0cy flag is set . this operation is illustrated in figure 13-10. figure 13-10. operation when ce reset coincides with btm0cy flag reading instruction consequently, if the btm0cy flag detection time interval coincides with the btm0cy flag setting time in a program that cyclically detects the btm0cy flag, ce reset is never effected. therefore, the following point must be noted. because one instruction cycle is 1.78 s (1/562.5 khz), a program that detects the btm0cy flag once, say, every 1125 instructions, reads the btm0cy flag every 1.78 s 1125 = 2 ms. because the timer time setting pulse is 100 ms at this time, if setting and detection of the btm0cy flag coincide once, ce reset is never effected. h btm0cy flag setting pulse btm0cy flag ce pin l h l 1.78 s skt1 btm0cy (peek ) skt1 btm0cy ce reset (skt ) 1 0 h btm0cy flag setting pulse btm0cy flag instruction embedded macro peek wr, . mf. btm0cy shr 4 skt wr, #. df. btm0cy and 000fh l 1 0 if btm0cy flag is read at this time, ce reset is effected delayed once. originally, program is started from address 0000h here. however, ce reset is not effected because it happens to coincide with program that reads btm0cy flag. skt1 btm0cy
pd17717, 17718, 17719 158 data sheet u12330ej2v0ds therefore, do not create a cyclic program that satisfies the following condition. t set 1125 = n (n: natural number) x t set : b tm0cy flag setting time x : cycle x step of instruction that reads btm0cy flag an example of a program that satisfies the above condition is shown below. do not create such a program. example processing a clr2 btm0ck1, btm0ck0 ; embedded macro ; sets btm0cy flag setting pulse to 100 ms loop: ; <1> skt1 btm0cy ; embedded macro br bbb aaa: 1121 steps br loop bbb: 1121 steps br loop because the btm0cy flag reading instruction in <1> is repeatedly executed every 1125 instruction in this example, ce reset is not effected if the btm0cy flag happens to be set at the timing of instruction in <1>.
159 pd17717, 17718, 17719 data sheet u12330ej2v0ds 13.3 timer 0 13.3.1 outline of timer 0 figure 13-11 shows the outline of timer 0. the timer 0 is used as timer (modulo mode) by comparing the count value with the previously set value after the basic clock (100 khz, 10 khz, 2 khz, and 1 khz) has counted by the 8-bit counter. the pulse width of the signal input from the tm0g pin can be measured (external gate counter). figure 13-11. outlines timer 0 remarks 1. tm0ck1 and tm0ck0 (bits 1 and 0 of timer 0 counter clock selection register: refer to figure 13-13 ) set a basic clock frequency. 2. tm0md (bit 0 of timer 0 mode selection register: refer to figure 13-14 ) selects the modulo counter and gate counter. 3. tm0goeg (bit 1 of timer 0 mode selection register: refer to figure 13-14 ) sets the open edge of an external gate. 4. tm0gceg (bit 2 of timer 0 mode selection register: refer to figure 13-14 ) sets the close edge of an external gate. 5. tm0ovf (bit 3 of timer 0 mode selection register: refer to figure 13-14 ) detects an overflow of timer 0 counter. 6. tm0res (bit 2 of timer 0 counter clock selection register: refer to figure 13-13 ) resets timer 0 counter. clock selection 4.5 mhz gate control p1a0/tm0g start/stop timer 0 counter (tm0c) tm0ck1 flag tm0ck0 flag tm0gceg flag tm0goeg flag tm0md flag tm0md flag coincidence detection circuit 8 tm0res flag dbf gate closed overflow sets irqtm0 flag tm0ovf flag dbf 8 timer 0 modulo register (tm0m)
pd17717, 17718, 17719 160 data sheet u12330ej2v0ds 13.3.2 clock selection, start/stop control, and gate control blocks figure 13-12 shows the configuration of these blocks. the clock selection block selects a basic clock to operate timer 0 counter. four types of basic clocks can be selected by using the tm0ck1 and tm0ck0 flags. figure 13-13 shows the configuration and function of each flag. the start/stop block controls the tm0md flag and open/close signal from the gate control block, and starts or stops the basic clock to be input to timer 0 counter by the tm0en flag. the gate control block sets the opening or closing conditions of the gate. it sets whether the gate is opened or closed by a rising or falling of the input signal, by using the tm0goeg and tm0gceg flags. this block also issues an interrupt request when the closing condition of the gate is detected. figure 13-14 shows the configuration and function of each flag. figure 13-12. configuration of clock selection, start/stop control, and gate control blocks selector 100 khz 10 khz 2 khz 1 khz tm0ck1 tm0ck0 clock selection divider 4.5 mhz start/stop timer 0 counter tm0en flag tm0md flag tm0md flag p1a0/tm0g tm0goeg tm0gceg gate control open/ close edge detection timer 0 interrupt
161 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 13-13. configuration of timer 0 counter clock selection register caution when the tm0res flag is read, 0 is always read. name flag symbol b 3 t m 0 e n b 2 t m 0 r e s b 1 t m 0 c k 1 b 0 t m 0 c k 0 address 2bh read/write r/w timer 0 counter clock selection power-on reset wdt&sp reset ce reset clock stop at reset 0 1 0 1 0 0 0 100 khz (10 s) 10 khz (100 s) 2 khz (500 s) 1 khz (1 ms) sets basic clock of timer 0 counter 0 0 0 0 0 0 0 0 1 1 does not change resets counter resets timer 0 counter 0 1 0 0 0 retained stops starts starts or stops timer 0 0 1
pd17717, 17718, 17719 162 data sheet u12330ej2v0ds 13.3.3 count block the count block counts the basic clock with an 8-bit timer 0 counter, reads the count value, and issues an interrupt request if the value of the timer 0 modulo register coincides with its value. timer 0 counter can be reset by the tm0res flag. the tm0ovf flag can detect an overflow of the counter. when an overflow occurs, an interrupt request can be issued. the value of the timer 0 counter can be read via data buffer. the value of the timer 0 modulo register can be written or read via data buffer. figure 13-14 shows the configuration of the timer 0 mode selection register. figure 13-15 shows the configuration of the timer 0 counter. figure 13-16 shows the configuration of the timer 0 modulo register. figure 13-14. configuration of timer 0 mode selection register name flag symbol b 3 t m 0 o v f b 2 t m 0 g c e g b 1 t m 0 g o e g b 0 t m 0 m d address 2ch read/write r/w timer 0 mode selection power-on reset wdt&sp reset ce reset clock stop at reset 0 1 0 0 0 modulo counter gate counter selects modulo counter or gate counter of timer 0 0 0 0 0 0 0 rising edge falling edge rising edge falling edge specifies edge of gate open input signal 0 1 0 0 0 retained specifies edge of gate close input signal 0 1 no overflow overflow detects timer 0 overflow 0 1
163 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 13-15. configuration of timer 0 counter reads count value of timer 0 data buffer dbf3 don't care dbf2 don't care name symbol address bit data dbf1 dbf0 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 timer 0 counter tm0c 1bh power-on reset wdt&sp reset ce reset clock stop 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 retained transfer data valid data 0 modulo mode reset if count value of timer 0 coincides with value of modulo counter. external gate mode resets counting to 00h if overflow occurs 0ffh 8 bits get put must not be executed at reset
pd17717, 17718, 17719 164 data sheet u12330ej2v0ds figure 13-16. configuration of timer 0 modulo register sets modulo data of timer 0 data buffer dbf3 don't care dbf2 don't care name symbol address bit data dbf1 dbf0 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 timer 0 modulo register tm0m 1ah power-on reset wdt&sp reset ce reset clock stop at reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 retained transfer data valid data 0 modulo mode issues interrupt request when value of modulo counter coincides with count value of timer 0. external gate mode does not issue interrupt request when value of modulo counter coincides with count value of timer 0. 0ffh 8 bits get put
165 pd17717, 17718, 17719 data sheet u12330ej2v0ds 13.3.4 example of using timer 0 (1) modulo counter mode the modulo counter mode is used for time management by generating timer 0 interrupt at fixed intervals. an example of a program is shown below. this program executes processing b every 500 s. tm0data dat 0032h ; modulo data = 50 start: br initial ; reset address ; interrupt vector address nop ; sio3 nop ; sio2 nop ; tm3 nop ; tm2 nop ; tm1 br int_tm0 ; tm0 nop ; int4 nop ; int3 nop ; int2 nop ; int1 nop ; int0 nop ; down edge of ce initial: initflg not tm0en, tm0res, not tm0ck1, not tm0ck0 ; (stop) , (reset) , (basic clock = 10 s) clr1 tm0md ; modulo mode mov dbf0, #(tm0mdata shr 0) and 0fh mov dbf1, #(tm0mdata shr 4) and 0fh put tm0m, dbf ; sets count data set1 iptm0 ; enables timer 0 interrupt ei set1 tm0en ; starts timer 0 loop: processing a br loop int_tm0: processing b ; timer 0 interrupt service ei reti ; return
pd17717, 17718, 17719 166 data sheet u12330ej2v0ds (2) gate counter mode the gate counter mode is used to count the width of a pulse input to the tm0g pin. an example of a program is shown below. in this program example, the width of the pulse input to the tm0g pin is counted from the falling edge to the falling edge. if the pulse width is 800 to 1200 s, processing c is executed; otherwise, processing b is executed. if the pulse width is 2560 s or more, processing d is executed. tm0800 dat 0050h ; count data = 80 tm01200 dat 0078h ; count data = 120 start: br initial ; reset address ; interrupt vector address nop ; sio3 nop ; sio2 nop ; tm3 nop ; tm2 nop ; tm1 br int_tm0 ; tm0 nop ; int4 nop ; int3 nop ; int2 nop ; int1 nop ; int0 nop ; down edge of ce initial: initflg not tm0en, tm0res, not tm0ck1, not tm0ck0 ; (stop) , (reset) , (basic clock = 10 s) initflg tm0gceg , tm0goeg , tm0md ; (falling close), (falling open), (gate counter) set1 tm0en ; start set1 iptm0 ; enables timer 0 interrupt ei loop: processing a br loop int_tm0: put dbfstk, dbf ; saves data buffer get dbf, tm0c initflg tm0en, tm0res skt1 tm0ovf ; detects overflow status (2560 s or more?) br aaa processing d br ei_reti aaa: sub dbf0, #tm0800 and 0fh subc dbf1, #tm0800 shr4 and 0fh skf1 cy ; 800 s or more? br bbb sub dbf0, #tm01200 and 0fh
167 pd17717, 17718, 17719 data sheet u12330ej2v0ds subc dbf1, #tm01200 shr4 and 0fh skt1 cy ; 1200 s or more? br bbb processing c br ei_reti bbb: processing b ei_reti: get dbf, dbfstk ; restores data buffer ei reti ; return end 13.3.5 error of timer 0 timer 0 has an error of up to 1 basic clock in the following cases. (1) on starting/stopping counter the counter is started or stopped by anding the open/close condition of the gate and tm0en flag setting condition. therefore, an error of 0 to +1 clocks occurs when the gate is opened or the tm0en flag is set, and an error of 1 to 0 clocks occurs when the gate is closed or the flag is reset. in all, an error of 1 count occurs. (2) on resetting counter operation an error of 0 to +1 clocks occurs when the counter is reset. (3) on selecting basic clock during counter operation an error of 0 to +1 clocks of the newly selected clock occurs. 13.3.6 cautions on using timer 0 timer 0 interrupt may occur simultaneously with the other timer interrupts and ce reset. if it is necessary to update the timer at ce reset, do not use timer 0, use basic timer 0 instead.
pd17717, 17718, 17719 168 data sheet u12330ej2v0ds 13.4 timer 1 13.4.1 outline of timer 1 figure 13-17 outlines timer 1. timer 1 counts the basic clock (100, 10, 2, or 1 khz) with an 8-bit counter, and compares the count value with a value set in advance. figure 13-17. outline of timer 1 remarks 1. tm1ck1 and tm1ck0 (bits 1 and 0 of timer 1 counter clock selection register: refer to figure 13-18 ) set the basic clock frequency. 2. tm1en (bit 3 of timer 1 counter clock selection register: refer to figure 13-18 ) starts or stops timer 1. 3. tm1res (bit 2 of timer 1 counter clock selection register: refer to figure 13-18 ) resets timer 1 counter. clock selection 4.5 mhz start/stop timre 1 counter (tm1c) tm1ck1 flag tm1ck0 flag tm1en flag coincidence detection circuit tm1res flag dbf timer 1 irqtm1 flag interrupt control dbf timer 1 modulo register (tm1m)
169 pd17717, 17718, 17719 data sheet u12330ej2v0ds 13.4.2 clock selection and start/stop control blocks the clock selection block selects a basic clock to operate timer 1 counter. four types of basic clocks can be selected by using the tm1ck1 and tm1ck0 flags. the start/stop block starts or stops the basic clock input to timer 1 by using the tm1en flag. figure 13-18 shows the configuration and function of each flag. 13.4.3 count block the count block counts the basic clock with timer 1 counter, reads the count value, and issues an interrupt request when its count value coincides with the value of the timer 1 modulo register. the timer 1 counter can be reset by the tm1res flag. the timer 1 counter is automatically reset when its value coincides with the value of the timer 1 modulo register. the value of the timer 1 counter can be read via data buffer. data can be written to the value of the timer 1 modulo register via data buffer. figure 13-18 shows the configuration of timer 1 counter clock selection register. figure 13-19 shows the configuration of the timer 1 counter. figure 13-20 shows the configuration of the timer 1 modulo register.
pd17717, 17718, 17719 170 data sheet u12330ej2v0ds figure 13-18. configuration of timer 1 counter clock selection register caution when the tm1res flag is read, 0 is always read. name flag symbol b 3 t m 1 e n b 2 t m 1 r e s b 1 t m 1 c k 1 b 0 t m 1 c k 0 address 2ah read/write r/w timer 1 counter clock selection power-on reset wdt&sp reset ce reset clock stop at reset 0 1 0 1 0 0 0 100 khz (10 s) 10 khz (100 s) 2 khz (500 s) 1 khz (1 ms) sets basic clock of timer 1 counter 0 0 0 0 0 0 0 0 1 1 does not change resets counter resets timer 1 counter (valid on writing) 0 1 0 0 0 retained stops starts starts or stops timer 1 0 1
171 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 13-19. configuration of timer 1 counter reads count value of timer 1 data buffer dbf3 don't care dbf2 don't care name symbol address bit data dbf1 dbf0 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 timer 1 counter tm1c 1dh power-on reset wdt&sp reset ce reset clock stop at reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 retained transfer data valid data 0 x count value 0ffh 8 bits get put must not be executed
pd17717, 17718, 17719 172 data sheet u12330ej2v0ds figure 13-20. configuration of timer 1 modulo register sets modulo data of timer 1 data buffer dbf3 don't care dbf2 don't care name symbol address bit data dbf1 dbf0 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 timer 1 modulo register tm1m 1ch power-on reset wdt&sp reset ce reset clock stop at reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 retained transfer data valid data 0 1 x setting prohibited modulo counter value 0ffh 8 bits get put
173 pd17717, 17718, 17719 data sheet u12330ej2v0ds 13.4.4 example of using timer 1 (1) modulo timer the modulo timer is used for time management by generating timer 1 interrupt at fixed intervals. an example of a program is shown below. this program executes processing b every 500 s. tm1data dat 0032h ; count data = 50 start: br initial ; reset address ; interrupt vector address nop ; sio3 nop ; sio2 nop ; tm3 nop ; tm2 br int_tm1 ; tm1 nop ; tm0 nop ; int4 nop ; int3 nop ; int2 nop ; int1 nop ; int0 nop ; down edge of ce initial: initflg not tm1en, tm1res, not tm1ck1, not tm1ck0 ; (stop) , (reset) , (basic clock = 10 s) mov dbf0, #tm1data mov dbf1, #tm1data shr4 and 0fh put tm1, dbf set1 tm1en ; start set1 iptm1 ; enables timer 1 interrupt ei loop: processing a br loop int_tm1: put dbfstk, dbf ; saves data buffer processing b get dbf, dbfstk ei reti ; return end
pd17717, 17718, 17719 174 data sheet u12330ej2v0ds 13.4.5 error of timer 1 timer 1 has an error of up to 1 basic clock in the following cases. (1) on starting/stopping counter the counter is started or stopped by setting the tm1en flag. therefore, an error of 0 to +1 clocks occurs when the tm1en flag is set, and an error of 1 to 0 clocks occurs when the flag is reset. in all, an error of 1 count occurs. (2) on resetting counter operation an error of 0 to +1 clocks occurs when the counter is reset. (3) on selecting basic clock during counter operation an error of 0 to +1 clocks of the newly selected clock occurs. 13.4.6 cautions on using timer 1 timer 1 interrupt may occur simultaneously with the other timer interrupts and ce reset. if it is necessary to update the timer at ce reset, do not use timer 1, use basic timer 0 instead.
175 pd17717, 17718, 17719 data sheet u12330ej2v0ds 13.5 timer 2 13.5.1 outline of timer 2 figure 13-21 outlines timer 2. timer 2 counts the basic clock (100, 10, 2, or 1 khz) with an 8-bit counter, and compares the count value with a value set in advance. figure 13-21. outline of timer 2 remarks 1. tm2ck1 and tm2ck0 (bits 1 and 0 of timer 2 counter clock selection register: refer to figure 13-22 ) set the basic clock frequency. 2. tm2en (bit 3 of timer 2 counter clock selection register: refer to figure 13-22 ) starts or stops timer 2. 3. tm2res (bit 2 of timer 2 counter clock selection register: refer to figure 13-22 ) resets timer 2 counter. clock selection 4.5 mhz start/stop timer 2 counter (tm2c) tm2ck1 flag tm2ck0 flag tm2en flag coincidence detection circuit tm2res flag dbf timer 2 irqtm2 flag interrupt control dbf timer 2 modulo register (tm2m)
pd17717, 17718, 17719 176 data sheet u12330ej2v0ds 13.5.2 clock selection and start/stop control blocks the clock selection block selects a basic clock to operate timer 2 counter. four types of basic clocks can be selected by using the tm2ck1 and tm2ck0 flags. the start/stop block starts or stops the basic clock input to timer 2 by using the tm2en flag. figure 13-22 shows the configuration and function of each flag. 13.5.3 count block the count block counts the basic clock with timer 2 counter, reads the count value, and issues an interrupt request when its count value coincides with the value of the timer 2 modulo register. the timer 2 counter can be reset by the tm2res flag. the timer 2 counter is automatically reset when its value coincides with the value of the timer 2 modulo register. the value of the timer 2 counter can be read via data buffer. data can be written to the value of the timer 2 modulo register via data buffer. figure 13-22 shows the configuration of timer 2 counter clock selection register. figure 13-23 shows the configuration of the timer 2 counter. figure 13-24 shows the configuration of the timer 2 modulo register.
177 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 13-22. configuration of timer 2 counter clock selection register caution when the tm2res flag is read, 0 is always read. name flag symbol b 3 t m 2 e n b 2 t m 2 r e s b 1 t m 2 c k 1 b 0 t m 2 c k 0 address 29h read/write r/w timer 2 counter clock selection power-on reset wdt&sp reset ce reset clock stop at reset 0 1 0 1 0 0 0 100 khz (10 s) 10 khz (100 s) 2 khz (500 s) 1 khz (1 ms) sets basic clock of timer 2 counter 0 0 0 0 0 0 0 0 1 1 does not change resets counter resets timer 2 counter (valid on writing) 0 1 0 0 0 retained stops starts starts or stops timer 2 0 1
pd17717, 17718, 17719 178 data sheet u12330ej2v0ds figure 13-23. configuration of timer 2 counter reads count value of timer 2 data buffer dbf3 don't care dbf2 don't care name symbol address bit data dbf1 dbf0 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 timer 2 counter tm2c 1fh power-on reset wdt&sp reset ce reset clock stop at reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 retained transfer data valid data 0 x count value 0ffh 8 bits get put must not be executed
179 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 13-24. configuration of timer 2 modulo register sets modulo data of timer 2 data buffer dbf3 don't care dbf2 don't care name symbol address bit data dbf1 dbf0 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 timer 2 modulo register tm2m 1eh power-on reset wdt&sp reset ce reset clock stop at reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 retained transfer data valid data 0 1 x setting prohibited modulo counter value 0ffh 8 bits get put
pd17717, 17718, 17719 180 data sheet u12330ej2v0ds 13.5.4 example of using timer 2 (1) modulo timer the modulo timer is used for time management by generating a timer 2 interrupt at fixed intervals. an example of a program is shown below. this program executes processing b every 500 s. tm2data dat 0032h ; count data = 50 start: br initial ; reset address ; interrupt vector address nop ; sio3 nop ; sio2 nop ; tm3 br int_tm2 ; tm2 nop ; tm1 nop ; tm0 nop ; int4 nop ; int3 nop ; int2 nop ; int1 nop ; int0 nop ; down edge of ce initial: initflg not tm2en, tm2res, not tm2ck1, not tm2ck0 ; (stop) , (reset) , (basic clock = 10 s) mov dbf0, #tm2data mov dbf1, #tm2data shr4 and 0fh put tm2, dbf set1 tm2en ; start set1 iptm2 ; enables timer 2 interrupt ei loop: processing a br loop int_tm2: put dbfstk, dbf ; saves data buffer initflg tm2en, tm2res ; resets and starts processing b get dbf, dbfstk ei reti ; return end
181 pd17717, 17718, 17719 data sheet u12330ej2v0ds 13.5.5 error of timer 2 timer 2 has an error of up to 1 basic clock in the following cases. (1) on starting/stopping counter the counter is started or stopped by setting the tm2en flag. therefore, an error of 0 to +1 clocks occurs when the tm2en flag is set, and an error of 1 to 0 clocks occurs when the flag is reset. in all, an error of 1 count occurs. (2) on resetting counter operation an error of 0 to +1 clocks occurs when the counter is reset. (3) on selecting basic clock during counter operation an error of 0 to +1 clocks of the newly selected clock occurs. 13.5.6 cautions on using timer 2 timer 2 interrupt may occur simultaneously with the other timer interrupts and ce reset. if it is necessary to update the timer at ce reset, do not use timer 2, use basic timer 0 instead.
pd17717, 17718, 17719 182 data sheet u12330ej2v0ds 13.6 timer 3 13.6.1 outline of timer 3 figure 13-25 outlines timer 3. timer 3 counts the basic clock (1.125 mhz or 112.5 khz selectable) with an 8-bit counter note , and compares the count value with a value set in advance. because timer 3 is multiplexed with a d/a converter, all the three d/a converter pins are automatically set in the general-purpose port mode when timer 3 is used. note a 9-bit or 8-bit counter can be selected for the d/a converter, but the 8-bit counter is automatically selected when the timer function is selected. figure 13-25. outline of timer 3 remarks 1. pwmck (bit 0 of pwm clock selection register: refer to figure 13-26 ) selects the output frequency of timer 3. 2. tm3sel (bit 3 of timer 3 control register: refer to figure 13-27 ) selects timer 3 or d/a converter. 3. tm3en (bit 1 of timer 3 control register: refer to figure 13-27 ) starts or stops counting by timer 3. 4. tm3res (bit 0 of timer 3 control register: refer to figure 13-27 ) controls resetting of timer 3 counter. clock selection 4.5 mhz start/stop timer 3 counter (tm3c) pwmck flag tm3en flag tm3sel flag coincidence detection circuit tm3res flag dbf irqtm3 flag interrupt control timer 3 modulo register ( tm3m )
183 pd17717, 17718, 17719 data sheet u12330ej2v0ds 13.6.2 clock selection block the clock of timer 3 is selected by the pwmck flag of the pwm clock selection register. figure 13-26 shows the configuration of the flag. figure 13-26. configuration of pwm clock selection register name flag symbol b 3 0 b 2 p w m b i t b 1 0 b 0 p w m c k address 26h read/write r/w pwm clock selection power-on reset wdt&sp reset ce reset clock stop r:retained at reset 0 1 0 0 r 0 4.4 khz (8 bits)/2.2 khz (9 bits) 440 hz (8 bits)/220 hz (9 bits) selects output frequency of timer 3 00 0 r 0 fixed to 0 fixed to 0 8 bits 9 bits 0 selects number of bits of pwm counter 0 1
pd17717, 17718, 17719 184 data sheet u12330ej2v0ds 13.6.3 start/stop control block the start/stop block starts or stops the basic clock to be input to timer 3 counter by using the tm3en flag. to control timer 3, timer 3 must be selected by the tm3sel flag. figure 13-27 shows the configuration of each flag. figure 13-27. configuration of timer 3 control register name flag symbol b 3 t m 3 s e l b 2 0 b 1 t m 3 e n b 0 t m 3 r e s address 28h read/write r/w timer 3 control 0 1 dose not change resets resets counter stop starts fixed to 0 starts or stops counter 0 1 d/a converter (pwm output) timer 3 selects timer 3 or d/a converter 0 1 power-on reset wdt&sp reset ce reset clock stop r:retained at reset 0 0 0 0 0 0 r 0 0 0 0 retained
185 pd17717, 17718, 17719 data sheet u12330ej2v0ds 13.6.4 count block the count block counts the basic clock with timer 3 and issues an interrupt request when the count value of timer 3 coincides with the value of the timer 3 modulo register. timer 3 counter can be reset by the tm3res flag. because the pwm data register 2 (pwmr2) and timer 3 modulo register (tm3m) are multiplexed, these registers cannot be used at the same time. when timer 3 is used, the pwm data register 1 (pwmr1) and pwm data register 0 (pwmr0) can be used as 9-bit data latches (refer to 15. d/a converter (pwm mode) ). figure 13-28. configuration of timer 3 modulo register note this register is multiplexed with the pwm data register 2. sets modulo data of timer 3 data buffer dbf3 dbf2 name symbol address bit data dbf1 dbf0 b 3 b 2 b 1 b 0 b 7 b 8 b 9 0 b 10 0 b 11 0 b 12 0 b 13 0 b 14 0 b 15 0 b 6 b 5 b 4 timer 3 modulo register note tm3m 46h power-on reset wdt&sp reset ce reset clock stop at reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 retained transfer data valid data 0 x modulo counter value fixed to 0 1ffh 16 bits get put
pd17717, 17718, 17719 186 data sheet u12330ej2v0ds 13.6.5 example of using timer 3 an example of a program using timer 3 (multiplexed with pwm) is given below. this program executes processing b every 888 s. tm3data dat 0064h ; count data = 100 start: br initial ; reset address ; interrupt vector address nop ; sio3 nop ; sio2 br int_tm3 ; tm3 nop ; tm2 nop ; tm1 nop ; tm0 nop ; int4 nop ; int3 nop ; int2 nop ; int1 nop ; int0 nop ; down edge of ce initial: initflg not pwmsel2 , not pwmsel1 , not pwmsel0 ; (general-purpose port), (general-purpose port), (general-purpose port) initflg not pwmbit, pwmck ; ( 8bit ), (440 hz) initflg tm3sel , not tm3en, tm3res ; (timer 3 mode), (stop) , (reset) mov dbf0, #tm3data mov dbf1, #tm3data shr4 and 0fh put tm3m, dbf set1 tm3en ; start set1 iptm3 ; enables timer 3 interrupt ei loop: processing a br loop int_tm3: put dbfstk, dbf ; saves data buffer processing b get dbf, dbfstk ei reti ; return end
187 pd17717, 17718, 17719 data sheet u12330ej2v0ds 13.6.6 error of timer 3 timer 3 has an error of up to 1 basic clock in the following cases. (1) on starting/stopping counter the counter is started or stopped by setting the tm3en flag. therefore, an error of 0 to +1 clocks occurs when the tm3en flag is set, and an error of 1 to 0 clocks occurs when the flag is reset. in all, an error of 1 count occurs. (2) on resetting counter operation an error of 0 to +1 clocks occurs when the counter is reset. (3) on selecting basic clock during counter operation an error of 0 to +1 clocks of the newly selected clock occurs. 13.6.7 cautions on using timer 3 timer 3 interrupt may occur simultaneously with the other timer interrupts and ce reset. if it is necessary to update the timer at ce reset, do not use timer 3, use basic timer 0 instead. when timer 3 is used, the three output port pins multiplexed with the d/a converter pins, p1b2/pwm2 through p1b0/pwm0, are automatically set in the general-purpose output port mode.
pd17717, 17718, 17719 188 data sheet u12330ej2v0ds 13.6.8 status at reset (1) at power-on reset the p1b2/pwm2 through p1b0/pwm0 pins are set in the general-purpose output port mode. the output value is low level . the value of each pwm data register (including the timer 3 modulo register) is 1ffh . (2) at wdt&sp reset the p1b2/pwm2 through p1b0/pwm0 pins are set in the general-purpose output port mode. the output value is low level . the value of each pwm data register (including the timer 3 modulo register) is 1ffh . (3) on execution of clock stop instruction the p1b2/pwm2 through p1b0/pwm0 pins are set in the general-purpose output port mode. the output value is the previous contents of the output latch . the value of each pwm data register (including the timer 3 modulo register) is 1ffh . (4) at ce reset the previous status is retained. that is, if the d/a converter is being used, the pwm output is retained as is. if timer 3 is being used, counting continues. while timer 3 is being used, the di status is set (in which all interrupts are disabled). (5) in halt status the previous status is retained. that is, if the d/a converter is being used, the pwm output is retained as is. if timer 3 is being used, counting continues.
189 pd17717, 17718, 17719 data sheet u12330ej2v0ds 14. a/d converter 14.1 outline of a/d converter figure 14-1 outlines the a/d converter. the a/d converter converts an analog voltage input to the ad5 to ad0 pins into an 8-bit digital signal. two modes can be selected by using the adcmd flag: software mode and hardware mode. in the software mode, a voltage input to a pin is compared with an internal reference voltage, and the result of the comparison is detected by the adccmp flag. by judging this result in software and by sequentially selecting reference voltages, the a/d converter can be used as a successive approximation a/d converter. in the hardware mode, reference voltages are automatically selected, and the input voltage is directly detected as 8-bit digital data. figure 14-1. outline of a/d converter remarks 1. adcch2 through adcch0 (bits 2 through 0 of a/d converter channel selection register: refer to figure 14-3 ) select pins used for the a/d converter. 2. adccmp (bit 0 of a/d converter mode selection register: refer to figure 14-5 ) detects the result of comparison. 3. adcstt (bit 1 of a/d converter mode selection register: refer to figure 14-5 ) detects the operating status. 4. adcmd (bit 2 of a/d converter mode selection register: refer to figure 14-5 ) selects software or hardware mode. p1c3/ad5 p1c2/ad4 p0d3/ad3 p0d2/ad2 p0d1/ad1 p0d0/ad0 adcch2 flag adcch1 flag adcch0 flag input selection block compare voltage generation block r-string d/a converter dbf adcmd flag adccmp flag adcstt flag start/stop control block compare block
pd17717, 17718, 17719 190 data sheet u12330ej2v0ds 14.2 input selection block figure 14-2 shows the configuration of the input selection block. the input selection block selects a pin to be used by using the adcch2 through adcch0 flags. only one pin can be used for the a/d converter. when one of the p0d0/ad0 through p0d3/ad3, p1c2/ad4, and p1c3/ ad5 pins is selected, the other five pins are forcibly set in the input port mode. the p0d0/ad0 through p0d3/ad3 pins can be connected to a pull-down resistor if so specified by the p0dpl0 through p0dpld3 flags. to use the p0d0/ad0 through p0d3/ad3 pins for the a/d converter, therefore, disconnect their pull-down resistors to correctly detect an external input analog voltage. figure 14-3 shows the configuration of the a/d converter channel selection register. figure 14-2. configuration of input selection block p1c3/ad5 p1c2/ad4 p0d3/ad3 p0d2/ad2 p0d1/ad1 p0d0/ad0 selector each i/o port adcch2 adcch1 adcch0 compare block v adcin
191 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 14-3. configuration of a/d converter channel selection register name flag symbol b 3 0 b 2 a d c c h 2 b 1 a d c c h 1 b 0 a d c c h 0 address 24h read/write r/w a/d converter channel selection power-on reset wdt&sp reset ce reset clock stop at reset 0 1 0 1 0 1 0 1 0 0 a/d converter not used (general-purpose input port) p0d0/ad0 pin p0d1/ad1 pin p0d2/ad2 pin p0d3/ad3 pin p1c2/ad4 pin p1c3/ad5 pin setting prohibited fixed to 0 selects pin used for a/d converter 00 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 retained retained
pd17717, 17718, 17719 192 data sheet u12330ej2v0ds 14.3 compare voltage generation and compare blocks figure 14-4 shows the configuration of the compare voltage generation block and compare block. the compare voltage generation block switches a tap decoder according to the 8-bit data set to the a/d converter reference voltage setting register and generates 256 different of compare voltages v adcref . in other words, this block is an r-string d/a converter. the supply voltage to this r-string d/a converter is the same as the supply voltage v dd of the device. the compare block compares voltage v adcin input from a pin with compare voltage v adcref . comparison can be made in two modes, software mode and hardware mode, which can be selected by the adcmd flag. in the software mode, a compare voltage is set to the a/d converter reference voltage setting register by software, and one set compare voltage is compared with the input voltage, and the result of the comparison is detected by the adccmp flag. in the hardware mode, once comparison has been started, the hardware automatically changes the value of the a/d converter reference voltage setting register. on completion of the comparison, the value of the a/d converter reference voltage setting register is read and is loaded as an 8-bit data. figures 14-5 and 14-6 show the configuration of each flag and a/d converter reference voltage setting register. figure 14-4. configuration of compare voltage generation and compare blocks dbf tap decoder 0 1 2 254 255 v dd a/d converter reference voltage setting register (adcr) 1 2 rr r 3 2 r soft/hard, start/stop control block adcmd flag adcstt flag adccmp flag comparator ? + 2 pf 1/2 v dd v adcin v adcref
193 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 14-5. configuration of a/d converter mode selection register notes 1. a/d conversion under execution is stopped if 0 is written to this bit. 2. a/d operation is started in the hardware mode when 1 is written to this bit. in the software mode, operation is started as soon as data has been written (by the put instruction) to the a/d converter reference voltage setting register (adcr). name flag symbol b 3 0 b 2 a d c m d b 1 a d c s t t b 0 a d c c m p address 25h read/write r/w a/d converter mode selection power-on reser wdt&sp reser ce reser clock stop r:retained at reset 0 1 0 0 0 r v adcin < v adcref v adcin > v adcref detects result of comparison by a/d converter 00 0 r r end of conversion conversion in progress software mode note 1 hardware mode note 2 detects operating status of a/d converter in hardware mode 0 1 0 0 0 0 selects compare mode of a/d converter and starts or stops a/d converter 0 1 fixed to 0
pd17717, 17718, 17719 194 data sheet u12330ej2v0ds figure 14-6. configuration of a/d converter reference voltage setting register note 0 in the hardware mode. sets or reads compare voltage v adcref of a/d converter in software mode: sets compare voltage in hardware mode: reads result of comparison data buffer dbf3 don't care dbf2 don't care name symbol address bit data dbf1 dbf0 b 3 b 2 b 1 b 0 b 7 b 6 b 5 b 4 a/d converter reference volfage setting register adcr 02h power-on reset wdt&sp reset ce reset clock stop at reset 0 0 retained note retained note transfer data valid data 0 x x-0.5 256 v adcref = 0 v v adcref = v dd (v) ffh 8 bits get put
195 pd17717, 17718, 17719 data sheet u12330ej2v0ds 14.4 comparison timing chart 14.4.1 in software mode comparison is completed three instructions after data has been set (by the put instruction) to the a/d converter reference voltage setting register (adcr). figure 14-7 shows the timing chart. figure 14-7. timing chart of comparison by a/d converter 14.4.2 in hardware mode when the adcmd flag is set to 1 , a/d conversion is started. the adcstt flag is set to 1 , and comparison is completed after 17 instructions have been executed. at this time, the adcstt flag is reset to 0 after 15 instructions have been executed after the adcmd flag was set to 1 . this is because execution time of two instructions is required to judge the status of the adcstt flag. for details, also refer to 14.5 using a/d converter . figure 14-8 shows the timing chart. figure 14-8. timing chart of comparison by a/d converter instruction cycle 1 0 put adcr, dbf 2 result of comparison 3 sample & hold adcstt fiag adccmp fiag comparison starts instruction cycle 1 2 1st 8th result of comparison 315 16 17 sample & hold adcstt flag reference voltage setting register a/d converter adcmd flag (=1) set. comparison starts end of comparison
pd17717, 17718, 17719 196 data sheet u12330ej2v0ds 14.5 using a/d converter 14.5.1 software mode the software mode is convenient for comparing one compare voltage. an example of a program in this mode is shown below. example to compare input voltage v adcin of ad0 pin with compare voltage v adcref (127.5/256 v dd ), and branch to aaa if v adcin < v adcref , or to bbb if v adcin > v adcref adcr7 flg 0.0eh.3 ; defines each bit of dbf as adcr data setting flag adcr6 flg 0.0eh.2 adcr5 flg 0.0eh.1 adcr4 flg 0.0eh.0 adcr3 flg 0.0fh.3 adcr2 flg 0.0fh.2 adcr1 flg 0.0fh.1 adcr0 flg 0.0fh.0 bank15 initflg not p0dpld3, not p0dpld2, not p0dpld1, p0dpld0 ; disconnects pull-down resistor of p0d0 pin bank0 initflg not adcch2, not adcch1, adcch0 ; selects ad0 pin for a/d converter clr1 adcmd ; sets software mode initflg adcr7, not adcr6, not adcr5, not adcr4 ; initflg not adcr3, not adcr2, not adcr1, not adcr0 ; put adcr, dbf ; sets compare voltage v adcref nop ; waits for duration of three instructions nop ; nop ; skt1 adccmp ; judges result of comparison br aaa br bbb 14.5.2 hardware mode here is a program example: example to detect the value of analog input roltage v adcin of ad0 pin. bank15 initflg not p0dpld3, not p0dpld2, not p0dpld1, p0dpld0 ; disconnects pull-down resistor of p0d0 pin bank0 initflg not adcch2, not adcch1, adcch0 ; selects ad0 pin for a/d converter set1 adcmd ; sets hardware mode and starts conversion loop: skt1 adcstt ; detects end of a/d conversion ; embedded macro instruction ;peek wr, .mf. adcstt shr4 and 0fh ;skt1 wr,#.df.adcstt and 0fh br loop ; conversion in progress get dbf,adcr ; stores result of conversion to dbf
197 pd17717, 17718, 17719 data sheet u12330ej2v0ds 14.6 cautions on using a/d converter 14.6.1 cautions on selecting a/d converter pin when one of the p0d0/ad0 through p0d3/ad3, p1c2/ad4, and p1c3/ad5 pins is selected, the other five pins are forcibly set in the input port mode. the p0d0/ad0 through p0d3/ad3 pins can be connected to a pull- down resistor if so specified by the p0dpl0 through p0dpld3 flags in bank 15. to use the p0d0/ad0 through p0d3/ad3 pins for the a/d converter, therefore, disconnect their pull-down resistors to correctly detect an external input analog voltage. 14.7 status at reset 14.7.1 at power-on reset all the p0d0/ad0 through p0d3/ad3, p1c2/ad4, and p1c3/ad5 pins are set in the general-purpose input port mode. the p0d0 through p0d3 pins are connected with a pull-down resistor. 14.7.2 at wdt&sp reset all the p0d0/ad0 through p0d3/ad3, p1c2/ad4, and p1c3/ad5 pins are set in the general-purpose input port mode. the p0d0 through p0d3 pins are connected with a pull-down resistor. 14.7.3 at ce reset the status of the pin selected for the a/d converter is retained as is. the previous status of the pull-down resistor of the p0d0 through p0d3 pins is retained. 14.7.4 on execution of clock stop instruction the status of the pin selected for the a/d converter is retained as is. the previous status of the pull-down resistor of the p0d0 through p0d3 pins is retained. 14.7.5 in halt status the status of the pin selected for the a/d converter is retained as is. the previous status of the pull-down resistor of the p0d0 through p0d3 pins is retained.
198 pd17717, 17718, 17719 data sheet u12330ej2v0ds 15. d/a converter (pwm mode) 15.1 outline of d/a converter figure 15-1 outlines the d/a converter. the d/a converter outputs a signal whose duty factor is varied by means of pwm (pulse width modulation). by connecting an external lowpass filter to the d/a converter, a digital signal can be converted into an analog signal. each pin of the d/a converter can output a variable-duty signal independently of the others. whether an 8-bit counter or 9-bit counter is used for the d/a converter can be specified by software. when the 8-bit counter is selected, two output frequencies, 4.4 khz and 440 hz can be selected, and the duty factor of the output signal can be varied in 256 steps. when the 9-bit counter is selected, two output frequencies, 2.2 khz and 220 hz, can be selected, and the duty factor can be varied in 512 steps. when the d/a converter is not used, it can be used as timer 3, which counts the basic clock (1.125 or 0.1125 mhz) with an 8-bit counter. for the details of timer 3, refer to 13. timer 3 . figure 15-1. outline of d/a converter remarks 1. pwm2sel through pwm0sel (bits 2 through 0 of pwm/general-purpose port pin function selection register: refer to figure 15-4 ) select a general-purpose output port of d/a converter. 2. pwmbit (bit 2 of pwm clock selection register: refer to figure 15-2 ) selects the number of bits (8 or 9 bits) of the pwm counter. 3. pwmck (bit 0 of pwm clock selection register: refer to figure 15-2 ) selects the output frequency of pwm timer. 4. tm3sel (bit 3 of timer 3 control register: refer to figure 15-5 ) selects timer 3 or d/a converter. 5. tm3res (bit 0 of timer 3 control register: refer to figure 15-5 ) controls resetting of timer 3 counter. p1b0/pwm0 p1b1/pwm1 p1b2/pwm2 pwm0sel flag dbf dbf dbf multiplexed with timer 3 duty setting block tm3sel flag tm3res flag res f pwm irqtm3 comparator comparator comparator pwmbit pwmck clock generation block 9-bit or 8-bit counter pwm data register 0 (pwmr0) pwm data register 1 (pwmr1) pwm data register 2 (pwmr2) output selection block output selection block output selection block pwm1sel flag pwm2sel flag
199 pd17717, 17718, 17719 data sheet u12330ej2v0ds 15.2 pwm clock selection register the pwm clock selection register specifies whether the pwm counter is used as an 8-bit counter or 9-bit counter when the d/a converter is used for pwm output. figure 15-2 shows the configuration of the pwm clock selection register. figure 15-2. configuration of pwm clock selection register name flag symbol b 3 0 b 2 p w m b i t b 1 0 b 0 p w m c k address 26h read/write r/w pwm clock selection power-on reset wdt&sp reset ce reset clock stop r: retained at reset 0 1 0 0 r 0 4.4 khz (8 bits) /2.2 khz (9 bits) 440 hz (8 bits) /220 hz (9 bits) selects output frequency of timer 3 00 0 r 0 fixed to 0 fixed to 0 8 bits 9 bits 0 selects number of bits of pwm counter 0 1
200 pd17717, 17718, 17719 data sheet u12330ej2v0ds 15.3 pwm output selection block the output selection block specifies whether each output pin of the d/a converter is used for the d/a converter or as a general-purpose output port, by using the pwm2sel through pwm0sel flags of the pwm/general-purpose port pin function selection register. figure 15-3 shows the configuration of the output selection block, and figure 15-4 shows the configuration of the pwm/general-purpose port pin function selection register. each pin can be changed between the d/a converter mode and general-purpose output port mode independently of the others. because each output pin is an n-ch open-drain output pin, an external pull-up resistor is necessary. when the d/a converter is used as timer 3, the p1b2/pwm2 through p1b0/pwm0 pins are automatically set in the general-purpose output port mode, regardless of the values set to the pwm2sel through pwm0sel flags. figure 15-3. configuration of output selection block pwm2sel through pwm0sel flags tm3sel comparator output output latch 1 0 each output pin
201 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 15-4. configuration of pwm/general-purpose port pin function selection register name flag symbol b 3 0 b 2 p w m 2 s e l b 1 p w m 1 s e l b 0 p w m 0 s e l address 27h read/write r/w pwm/general-purpose port pin function selection power-on reset wdt&sp reset ce reset clock stop retained at reset 0 1 0 0 0 general-purpose output port d/a converter selects function of p1b0/pwm0 pin 00 0 0 general-purpose output port d/a converter general-purpose output port d/a converter selects function of p1b1/pwm1 pin 0 1 0 0 0 selects function of p1b2/pwm2 pin 0 1 fixed to 0
202 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 15-5. configuration of timer 3 control register name flag symbol b 3 t m 3 s e l b 2 0 b 1 t m 3 e n b 0 t m 3 r e s address 28h read/write r/w timer 3 control 0 1 does not change resets resets counter stops starts fixed to 0 starts or stops counter 0 1 d/a converter (pwm output) timer 3 selects timer 3 or d/a converter 0 1 power-on reset wdt&sp reset ce reset clock stop r: retained at reset 0 0 0 0 0 0 r 0 0 0 0 retained
203 pd17717, 17718, 17719 data sheet u12330ej2v0ds 15.4 duty setting block 15.4.1 pwm duty with 8-bit counter selected the duty setting block compares the value set to each pwm data register (pwmr2 to pwmr0) with the value of the basic clock counted by each 8-bit counter. if the value of the pwm data register is greater, the block outputs a high level. if the value of the pwm data register is less, it outputs a low level. where the value set to the pwm data register is ?? therefore, the duty factor can be calculated by the following expression. duty: d = x + 0.25 100% 256 remark 0.25 is an offset, and a high level is output even where x = 0. data is set to each pwm data register for each pin via data buffer (dbf). however, the same basic clock, pwm counter, and output frequency must be selected for each pin. this means that each pin cannot output a duty factor of a different cycle independently of the others. because the basic clock frequency is 1.125 or 0.1125 mhz, the frequency and cycle of the output signal can be calculated as follows. (1) where output frequency is 4.4 khz and basic clock frequency is 1.125 mhz frequency: f = 1.125 mhz = 4.3945 khz 256 cycle: t = 256 = 227.56 s 1.125 mhz (2) where output frequency is 440 hz and basic clock frequency is 0.1125 mhz frequency: f = 0.1125 mhz = 439.45 hz 256 cycle: t = 256 = 2.2756 ms 0.1125 mhz because the duty setting register of the pwm data registers and timer 3 modulo register are the same register, they cannot be used at the same time. when timer 3 is used, pwm data registers 1 and 0 can be used as 8-bit data latches.
204 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 15-6. configuration of pwm data registers (with 8-bit counter selected) note this register is multiplexed with timer 3 modulo register. sets pwm output duty of each pin data buffer dbf3 dbf2 name symbol address bit data dbf1 dbf0 b 3 b 2 b 1 b 0 b 7 b 8 0 b 9 0 b 10 0 b 11 0 b 12 0 b 13 0 b 14 0 b 15 0 b 6 b 5 b 4 pwm data register 2 note pwmr2 46h power-on reset wdt&sp reset ce reset clock stop at reset retained 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 transfer data valid data 0 x duty: d = 100 % fixed to ? ffh 16 bits get put name symbol address bit data b 3 b 2 b 1 b 0 b 7 b 8 0 b 9 0 b 10 0 b 11 0 b 12 0 b 13 0 b 14 0 b 15 0 b 6 b 5 b 4 pwm data register 1 pwmr1 45h valid data get put name symbol address bit data b 3 b 2 b 1 b 0 b 7 b 8 0 b 9 0 b 10 0 b 11 0 b 12 0 b 13 0 b 14 0 b 15 0 b 6 b 5 b 4 pwm data register 0 pwmr0 44h valid data get put x + 0.25 256
205 pd17717, 17718, 17719 data sheet u12330ej2v0ds 15.4.2 pwm duty with 9-bit counter selected the duty setting block compares the value set to each pwm data register (pwmr2 to pwmr0) with the value of the basic clock counted by each 9-bit counter. if the value of the pwm data register is greater, the block outputs a high level. if the value of the pwm data register is less, it outputs a low level. where the value set to the pwm data register is x , therefore, the duty factor can be calculated by the following expression. duty: d = x + 0.25 100% 512 remark 0.25 is an offset, and a high level is output even where x = 0. data is set to each pwm data register for each pin via data buffer (dbf). however, the same basic clock, pwm counter, and output frequency must be selected for each pin. this means that each pin cannot output a duty factor of a different cycle independently of the others. because the basic clock frequency is 1.125 or 0.1125 mhz, the frequency and cycle of the output signal can be calculated as follows. (1) where output frequency is 2.2 khz and basic clock frequency is 1.125 mhz frequency: f = 1.125 mhz = 2.197 khz 512 cycle: t = 512 = 455.11 s 1.125 mhz (2) where output frequency is 220 hz and basic clock frequency is 0.1125 mhz frequency: f = 0.1125 mhz = 219.73 hz 512 cycle: t = 512 = 4.5511 ms 0.1125 mhz because the duty setting register of the pwm data registers and timer 3 modulo register are the same register, they cannot be used at the same time. when timer 3 is used, pwm data registers 1 and 0 can be used as 8-bit data latches.
206 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 15-7. configuration of pwm data registers (with 9-bit counter selected) note this register is multiplexed with timer 3 modulo register. sets pwm output duty of each pin data buffer dbf3 dbf2 name symbol address bit data dbf1 dbf0 b 3 b 2 b 1 b 0 b 7 b 8 b 9 0 b 10 0 b 11 0 b 12 0 b 13 0 b 14 0 b 15 0 b 6 b 5 b 4 pwm data register 2 note pwmr2 46h power-on reset wdt&sp reset ce reset clock stop at reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 retained transfer data valid data 0 x duty: d = 100 % fixed to ? 1ffh 16 bits get put name symbol address bit data b 3 b 2 b 1 b 0 b 7 b 8 b 9 0 b 10 0 b 11 0 b 12 0 b 13 0 b 14 0 b 15 0 b 6 b 5 b 4 pwm data register 1 pwmr1 45h valid data get put name symbol address bit data b 3 b 2 b 1 b 0 b 7 b 8 b 9 0 b 10 0 b 11 0 b 12 0 b 13 0 b 14 0 b 15 0 b 6 b 5 b 4 pwm data register 0 pwmr0 44h valid data get put x + 0.25 512
207 pd17717, 17718, 17719 data sheet u12330ej2v0ds 15.5 clock generation block the clock generation block outputs a basic clock to set the duty factor of each output signal. two output frequencies, 1.125 mhz and 112.5 khz, can be selected. 15.6 d/a converter output wave (1) shows the relationship between the duty factor and output wave. (2) shows the output wave of each pin. each output pin has a phase different from the others. (1) duty and output wave (a) with 8-bit counter and 4.4 khz selected (b) with 8-bit counter and 440 hz selected 2.22 s x = 0 x = 1 x = 2 x = 255 6.67 s 8.88 s 8.88 s 2.2756 ms ? 222 ns x = 0 x = 1 x = 2 x = 255 667 ns 888 ns 888 ns 227.56 s
208 pd17717, 17718, 17719 data sheet u12330ej2v0ds (c) with 9-bit counter and 2.2 khz selected (d) with 9-bit counter and 220 hz selected (2) each pin and output wave (a) with 8-bit counter and 4.4 khz selected 222 ns x = 0 x = 1 x = 2 x = 511 667 ns 888 ns 888 ns 455.11 s 2.22 s x = 0 x = 1 x = 2 x = 511 6.67 s 8.88 s 8.88 s 4.5511 ms 222 ns pwm0 (x = 0) pwm1 (x = 0) pwm2 (x = 0) 222 ns 222 ns 227.56 s 227.56 s 227.56 s
209 pd17717, 17718, 17719 data sheet u12330ej2v0ds (b) with 8-bit counter and 440 hz selected (c) with 9-bit counter and 2.2 khz selected (d) with 9-bit counter and 220 hz selected 2.22 s pwm0 (x = 0) pwm1 (x = 0) pwm2 (x = 0) 2.22 s 2.22 s 2.2756 ms 2.2756 ms 2.2756 ms 222 ns pwm0 (x = 0) pwm1 (x = 0) pwm2 (x = 0) 222 ns 222 ns 455.11 s 455.11 s 455.11 s 2.22 s pwm0 (x = 0) pwm1 (x = 0) pwm2 (x = 0) 2.22 s 2.22 s 4.5511 ms 4.5511 ms 4.5511 ms
210 pd17717, 17718, 17719 data sheet u12330ej2v0ds 15.7 example of using d/a converter an example of a program using the d/a converter is shown below. example this program increments the duty factor of the pwm1 pin every 1 second. pwm1data dat 0000h initial: initflg not pwm2sel, not pwm1sel, not pwm0sel ; (general-purpose port), (general-purpose port), (general-purpose port) initflg pwmbit , not pwmck ; (9-bit counter), (1.125 mhz) loop0: bank1 clr1 p1b1 bank0 clr1 tm3sel ; selects d/a converter mov dbf2, #pwm1data shr 8 and 0fh mov dbf1, #pwm1data shr 4 and 0fh mov dbf0, #pwm1data and 0fh set1 pwm1sel ; sets pwm1/p1b1 pin in pwm output port mode loop1: ; duty: 0.25/512 to 511.25/512 (pwm output) put pwm1r, dbf get2 tm3res, tm3en ; resets and starts counter waits for 1 second get dbf, pwm1r add dbf0, #1 addc dbf1, #0 addc dbf2, #1 skge dbf2, #2 br loop1 loop2: ; port outputs high level bank1 set1 p1b1 bank0 clr1 pwm1sel ; sets pwm1/p1b1 pin in general-purpose output port mode waits for 1 second br loop0
211 pd17717, 17718, 17719 data sheet u12330ej2v0ds 15.8 status at reset 15.8.1 at power-on reset the p1b0/pwm0 through p1b2/pwm2 pins are set in the general-purpose output port mode. the output value is low level . the value of each pwm data register (including the timer 3 modulo register) is 1ffh . 15.8.2 at wdt&sp reset the p1b0/pwm0 through p1b2/pwm2 pins are set in the general-purpose output port mode. the output value is low level . the value of each pwm data register (including the timer 3 modulo register) is 1ffh . 15.8.3 at ce reset the p1b0/pwm2 through p1b2/pwm2 pins retain the previous status. that is, if the d/a converter is being used, the pwm output is retained as is. if timer 3 is being used, counting continues. 15.8.4 on execution of clock stop instruction the p1b0/pwm0 through p1b2/pwm2 pins are set in the general-purpose output port mode. the output value is the previous contents of the output latch . the value of each pwm data register (including the timer 3 modulo register) is 1ffh . 15.8.5 in halt status the p1b0/pwm0 through p1b2/pwm2 pins retain the previous status. that is, if the d/a converter is being used, the pwm output is retained as is. if timer 3 is being used, counting continues.
212 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16. serial interface 16.1 outline of serial interface figure 16-1 shows the outline of the serial interface. table 16-1 shows classification and communication modes of the serial interface. the serial interface consists of serial interface 2 (sio2) and serial interface 3 (sio3). figure 16-1. outline of serial interface sda/p0a3 scl/p0a2 sck2/p0a1 so2/p0a0 si2/p0b3 sck/p2d2 sb0/p2d0 sb1/p2d1 presettable shift register 2 (sio2sfr) clock control block 4.5 mhz interrupt control block irqsio2 flag serial interface 2 sck3/p0b2 so3/txd/p0b1 si3/rxd/p0b0 transmit shift register (sio3txs) clock control block 4.5 mhz interrupt control block irqsio3 flag serial interface 3 receive buffer register (sio3rxb) receive shift register i/o control i/o control
213 pd17717, 17718, 17719 data sheet u12330ej2v0ds table 16-1. classification and communication modes of serial interface channel communication mode pin used serial interface 2 i 2 c (inter ic) bus mode p0a2/scl 2-wire serial i/o mode p0a3/sda sbi (serial bus interface) mode p2d0/sb0 p2d1/sb1 p2d2/sck 3-wire serial i/o mode p0a0/so2 p0a1/sck2 p0b3/si2 serial interface 3 3-wire serial i/o mode p0b0/si3 p0b1/so3 p0b2/sck3 uart p0b0/rxd p0b1/txd
214 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.2 serial interface 2 16.2.1 outline of serial interface 2 figure 16-2 shows the outline of serial interface 2. serial interface 2 can be used in the i 2 c bus, sbi, and 2-wire or 3-wire serial i/o modes. figure 16-2. outline of serial interface 2 scl/p0a2 sck2/p0a1 sck/p2d2 sda/p0a3 sb0/p2d0 sb1/p2d1 so2/p0a0 si2/p0b3 sio2cld flag sio2csie flag sio2md0 through 2 flags sio2clc flag clock i/o control block sio2tlc0 and 1 flags clock control block wait signal 4.5 mhz sio2wat0 and 1 flags clock counter wait control block sio2wat0 and 1 flags sio2wrel flag sio2wup flag interrupt control block sio2ackd flag sio2reld flag sio2cmdd flag sio2sic flag start/stop/ acknowledge detection block sio2csie flag sio2md0 through 2 flags data i/o control block sio2sfr out in sio2sva sio2coi flag sio2svam flag start/acknowledge control block sio2ackt flag sio2acke flag sio2bsye flag sio2relt flag sio2cmdt flag
215 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.2.2 control registers of serial interface 2 serial interface 2 is controlled by the following six registers: serial i/o2 operation mode register 0 serial i/o2 operation mode register 1 serial i/o2sbi register 0 serial i/o2sbi register 1 serial i/o2 interrupt timing specification register 0 serial i/o2 interrupt timing specification register 1
216 pd17717, 17718, 17719 data sheet u12330ej2v0ds (1) serial i/o2 operation mode register 0 figure 16-3 shows the configuration of the serial i/o2 operation mode register 0. this register controls the operation of serial interface 2, and select the clock to be used. figure 16-3. configuration of serial i/o2 operation mode register 0 caution read the sio2coi flag after completion of transfer. this flag is undefined during transfer. name flag symbol b 3 s i o 2 c s i e b 2 s i o 2 c o i b 1 s i o 2 t c l 1 b 0 s i o 2 t c l 0 address 0fh read/write r/w serial i/o2 operation mode register 0 power-on reset wdt & sp reset ce reset clock stop 0 0 0 0 0 1 0 1 93.75 khz 375 khz 281.25 khz 46.875 khz sets internal shift clock frequency does not coincide coincides coincidence signal from address comparator stops operation (wait status) enables operation controls operation of serial i/o2 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 at reset
217 pd17717, 17718, 17719 data sheet u12330ej2v0ds (2) serial i/o2 operation mode register 1 figure 16-4 shows the configuration of the serial i/o2 operation mode register 1. this register controls the operation of serial interface 2 and selects the clock to be used. figure 16-4. configuration of serial i/o2 operation mode register 1 caution set the sio2wup flag before starting address reception. name flag symbol b 3 s i o 2 w u p b 2 s i o 2 m d 2 b 1 s i o 2 m d 1 b 0 s i o 2 m d 0 address 0eh read/write r/w serial i/o2 operation mode register 1 power-on reset wdt & sp reset ce reset clock stop 0 0 0 0 0 1 slave operation (external clock input) master operation (internal clock output) sets direction of shift clock 3-wire serial i/o mode sbi mode (sb1) sbi mode (sb0) 2-wire serial i/o mode or i 2 c bus mode sets operation mode of serial i/o2 stops wake up enables wake up (used in sbi and i 2 c bus modes) controls wake-up function 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 sbi/i 2 c bus mode serial i/o mode external clock input internal clock output 0 1 0 1 at reset
218 pd17717, 17718, 17719 data sheet u12330ej2v0ds (3) serial i/o2sbi register 0 this register controls and detects the status of the serial bus interface. figure 16-5 shows the configuration of the serial i/o2sbi register 0. figure 16-5. configuration of serial i/o2sbi register 0 name flag symbol b 3 s i o 2 b s y e b 2 s i o 2 a c k d b 1 s i o 2 a c k e b 0 s i o 2 a c k t address 0dh read/write r/w serial i/o2 sbi register 0 power-on reset wdt & sp reset ce reset clock stop 0 0 0 0 0 1 automatically cleared after flag has been set acknowledge signal is output in synchronization with next clock if this bit is set after completion of transfer. controls trigger output of acknowledge signal stops automatic output of acknowledge signal (output by sio2ackt is possible). controls output of acknowledge signal acknowledge signal is not detected. acknowledge signal is detected (in synchronization with rising of clock). detects acknowledge signal 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 disables output of busy signal in synchronization with falling of clock immediately after clear instruction. control of synchronous busy signal output 0 before completion of transfer: after completion of transfer : 1 acknowledge signal is output in synchronization with 9th clock. acknowledge signal is output in synchronization with clock immediately after set instruction. unlike sio2ackt, this bit is not cleared automatically after output of acknowledge signal. outputs busy signal in synchronization with falling of clock after acknowledge signal. 1 at reset
219 pd17717, 17718, 17719 data sheet u12330ej2v0ds cautions 1. when using the sio2acke flag, set the flag until the falling of the 9th counting of clock scl during i 2 c bus operation. 2. when using the sio2ackt flag, clear sio2acke to 0 . during i 2 c bus operation, set the flag until the falling of the 9th counting of clock scl. 3. because the sio2ackt flag is automatically cleared after it has been set to 1 , it is always 0 when read.
220 pd17717, 17718, 17719 data sheet u12330ej2v0ds (4) serial i/o2sbi register 1 this register controls and detects the status of the serial bus interface. figure 16-6 shows the configuration of the serial i/o2sbi register 1. figure 16-6. configuration of serial i/o2sbi register cautions 1. the sio2cmdt flag is disabled from being set during serial transfer. 2. because the sio2cmdt flag is automatically cleared after it has been set to 1 , it is always 0 when read. 3. because the sio2relt flag is automatically cleared after it has been set to 1 , it is always 0 when read. name flag symbol b 3 s i o 2 c m d d b 2 s i o 2 r e l d b 1 s i o 2 c m d t b 0 s i o 2 r e l t address 0ch read/write r/w serial i/o2 sbi register 1 power-on reset wdt & sp reset ce reset clock stop 0 0 0 0 0 1 automatically cleared after flag has been set. sets so2 latch by setting flag. used to output bus release signal. controls trigger output of bus release signal automatically cleared after flag has been set. resets so2 latch by setting flag. used to output command signal. controls trigger output of command signal bus release signal is not detected. bus release signal is detected. detects bus release signal 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 command signal is not detected. command signal is detected. detects command signal 0 1 at reset
221 pd17717, 17718, 17719 data sheet u12330ej2v0ds (5) serial i/o2 interrupt timing specification register 0 this register controls and detects the status of the serial bus interface. figure 16-7 shows the configuration of the serial i/o2 interrupt timing specification register 0. figure 16-7. configuration of serial i/o2 interrupt timing specification register 0 caution writing this register is inhibited during serial transfer. name flag symbol b 3 b 2 s i o 2 c l d b 1 s i o 2 s i c b 0 s i o 2 s v a m address 0bh read/write r/w serial i/o2 interrupt timing specification register 0 power-on reset wdt & sp reset ce reset clock stop 0 0 0 0 0 1 bits 0 through 7 bits 1 through 7 bits of sio2sva register used as slave address interrupt occurs only on completion of serial transfer interrupt occurs on completion of serial transfer or on detection of bus release selects interrupt source of serial i/o2 p0a2/scl pin is low p0a2/scl pin is high detects p0a2/scl pin level 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 fixed to "0" 0 at reset
222 pd17717, 17718, 17719 data sheet u12330ej2v0ds (6) serial i/o2 interrupt timing specification register 1 this register controls and detects the status of the serial bus interface. figure 16-8 shows the configuration of the serial i/o2 interrupt timing specification register 1. figure 16-8. configuration of serial i/o2 interrupt timing specification register 1 name flag symbol b 3 s i o 2 c l c b 2 s i o 2 w r e l b 1 s i o 2 w a t 1 b 0 s i o 2 w a t 0 address 0ah read/write r/w serial i/o2 interrupt timing specification register 1 power-on reset wdt & sp reset ce reset clock stop 0 0 0 0 0 1 0 1 issues interrupt request at rising of 8th clock issues interrupt request at rising of 8th clock used in i 2 c bus mode (8-clock wait). issues interrupt request at rising of 8th clock of scl (master makes scl output low and waits after 8 clocks have been output. slave makes scl pin low and requests for wait after it has input 8 clocks). used in i 2 c bus mode (9 clock wait). issues interrupt request at rising of 9th clock of scl (master makes scl output low and waits after 9 clocks have been output. slave makes scl pin low and requests for wait after it has input 9 clocks). controls wait and interrupt wait released status releases wait status (flag is automatically cleared after wait status has been released.) wait release control (used in i 2 c bus mode) 0 1 0 0 0 0 0 0 0 0 0 0 0 0 p0a2/scl pin is not affected. p0a2/scl pin goes into high-impedance state. control of p0a2/scl pin level (used in i 2 c bus mode) 0 1 0 0 1 1 at reset
223 pd17717, 17718, 17719 data sheet u12330ej2v0ds cautions 1. the sio2wrel flag can be manipulated only in the wait status. because this flag is automatically cleared after it has been set to 1 , it is always 0 when read. 2. the sio2clc flag is set to 1 when a start/stop signal is created in the i 2 c bus mode. it is usually cleared to 0 . 3. the wait status set by sio2wat0 and sio2wat1 is released in the following sequence: sio2wrel = 1 data is written to sio2sfr. sio2csie = 0
224 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.2.3 presettable shift register 2 (sio2sfr) the presettable shift register 2 is an 8-bit register that is used to write serial out data and read serial in data. this register writes or reads data via data buffer. because the input pin and output pin are multiplexed to configure the bus in the 2-wire serial i/o, i 2 c bus, and sbi modes, write ffh to sio2sfr in the 2-wire serial i/o mode. in the i 2 c bus mode, set 1 to sio2bsye, and write ffh to sio2sfr. in the sbi mode, the device that is to receive data must write ffh to sio2sfr (except when the device receives address with 1 set to sio2wup). in the sbi mode, the busy signal can be released by writing data to sio2sfr. in this case, sio2bsye is not cleared to 0. figure 16-9 shows the configuration of the presettable shift register 2. figure 16-9. configuration of presettable shift register 2 peripheral register valid data dbf3 dbf2 dbf1 dbf0 data buffer transfer data don't care don't care 8 get put name symbol peripheral address sio2sfr 03h presettable shift register 2 b 7 m s b b 6 b 5 b 4 b 3 b 2 b 1 b 0 l s b setting of serial-out data and reading of serial-in data d7 d6 d5 d4 d3 d2 d1 d0 serial out serial in d7 d6 d5 d4 d3 d2 d1 d0
225 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.2.4 serial i/o2 slave address register (sio2sva) this is an 8-bit register that sets a slave address value when the microcontroller is connected to the serial bus as a slave device. a slave address is output to the slave devices connected to the master to select a specific slave. the two values (slave address output by the master and the value of sio2sva) are compared by the address comparator, and if they coincide, the slave having that slave address is selected. at this time, the sio2coi flag of the serial i/o2 operation mode register 0 is set to 1. in addition, the data of the high-order 7 bits with the lsb masked can be compared as an address by using the sio2svam flag of the serial i/o2 interrupt timing specification register. if coincidence is not detected during address reception, sio2reld of serial i/o2sbi register 1 is cleared to 0. if the sio2wup flag of the serial i/o2 operation mode register is 1, an interrupt request is issued only when coincidence is detected. this interrupt indicates that the master has requested communication. this register also detects an error when the device is used as the master or slave in the 2-wire serial i/o, i 2 c bus, or sbi mode. figure 16-10 shows the configuration of the serial i/o2 slave address register. figure 16-10. configuration of serial i/o2 slave address register peripheral register valid data dbf3 dbf2 dbf1 dbf0 data buffer transfer data don't care don't care 8 get put name symbol peripheral address sio2sva 04h serial i/o2 slave address register b 7 m s b b 6 b 5 b 4 b 3 b 2 b 1 b 0 l s b
226 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.2.5 operation of serial interface 2 the serial interface 2 has the following four operation modes: 3-wire serial i/o mode sbi mode 2-wire serial i/o mode i 2 c bus mode table 16-2 shows the setting of each pin by a control flag in each operation mode. table 16-2. setting status of each pin by each control flag (1/2) flag pin ssss communication s clock direction pin name p ppppppppp setting status of pin iiii mode i 0000000000 oooo o a aaaaaaabb 2222 2 b3b2b1b0b3 cmmw m iiiii sdda d ooooo i21t 0 32103 e1 1000 3-wire 0 external p0a1/sck2 0 external clock input serial i/o (slave) 1 general-purpose output port 1 internal 0 external clock input (master) 1 1 internal clock output p0a0/so2 0 general-purpose input port 1 0 serial output p0b3/si2 0 serial input 1 general-purpose output port 1 1 0 2-wire 0 external p0a2/scl 0 external clock input serial i/o (slave) 1 general-purpose output port 1 internal 0 general-purpose input port (master) 1 1 internal clock output p0a3/sda 0 serial input 1 0 serial output 111 i 2 c bus 0 external p0a2/scl 0 external clock input serial i/o (slave) 1 general-purpose output port 1 internal 0 general-purpose input port (master) 1 1 internal clock output p0a3/sda 0 serial input 1 0 serial output : don t care
227 pd17717, 17718, 17719 data sheet u12330ej2v0ds table 16-2. setting status of each pin by each control flag (2/2) flag pin ssss communication s clock direction pin name pppppp setting status of pin iiii mode i 222222 oooo o dddddd 2222 2 b2b1b0 cmmw m iii sdda d ooo i21t 0 210 e1 1100 sbi 0 external p2d2/sck 0 external clock input (when data is (slave) 1 general-purpose output port input to or 1 internal 0 general-purpose input port output from (master) 1 1 internal clock output sb0 pin) p2d0/sb0 0 serial input 1 0 serial output 0 1 0 sbi 0 external p2d2/sck 0 external clock input (when data is (slave) 1 general-purpose output port input to or 1 internal 0 general-purpose input port output from (master) 1 1 internal clock output sb1 pin) p2d1/sb1 0 serial input 1 0 serial output : don t care
228 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.2.6 3-wire serial i/o mode (1) outline of 3-wire serial i/o mode in the 3-wire serial i/o mode, communication is executed by using the sck2, si2, and so2 pins. table 16-3 outlines the 3-wire serial i/o mode. table 16-3. outline of 3-wire serial i/o mode pins used for sck2 pin (serial clock i/o pin) communication si2 pin (serial data input pin) so2 pin (serial data output pin) transmission/reception transmit data sequentially output from msb of shift register to data output pin in operation synchronization with fall of sck2 pin receive data value of data input pin is sequentially input from lsb of shift register in synchronization with rising of sck2 pin. transmission/reception master transmission/reception is started by setting transfer data to shift start register after 3-wire serial i/o master mode has been set. slave waits for clock from master with sck2 pin going into high-impedance state after 3-wire serial i/o slave mode has been set. interrupt issues interrupt request flag irqsio2 at rising edge of 8th count of clock. clock pin master stops output of sck2 pin at rising edge of 8th count and keeps sck2 pin high until next transmission/reception operation is started. slave goes into high-impedance state. figure 16-11. example of serial bus configuration in 3-wire serial i/o sck2 si2 so2 master slave sck2 so2 si2
229 pd17717, 17718, 17719 data sheet u12330ej2v0ds (2) timing chart figure 16-12 shows the timing chart in the 3-wire serial i/o mode. figure 16-12. timing chart in 3-wire serial i/o mode the so2 pin serves as a cmos output pin and outputs the status of the so2 latch. therefore, the so2 pin output status can be manipulated by setting the sio2relt and sio2cmdt flags. however, do not perform this manipulation during serial transfer. (3) signals figure 16-13 shows the operations of sio2relt and sio2cmdt. figure 16-13. operation of sio2relt and sio2cmdt so2 latch sio2relt sio2cmdt 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 starts transfer in synchronization with falling of sck2 end of transfer irqsio2 flag sck2 pin si2 pin so2 pin writing to shift register
230 pd17717, 17718, 17719 data sheet u12330ej2v0ds (4) program flowchart in 3-wire serial i/o mode a program flowchart example in the 3-wire serial i/o transmission mode is shown below. figure 16-14. example flowchart in 3-wire serial i/o transmission mode remark to execute a 3-wire serial i/o operation with the same setting as before, start from step <5>. <1> setting of pin (a) setting of data pin in 3-wire serial i/o mode set the i/o control mode of the data pin to 1 (output), and the port latch of the data pin to 0 . (b) setting of shift clock in 3-wire serial i/o mode set the i/o control mode of the shift clock to 1 (output), and the port latch of the shift clock to 1 . <2> setting 3-wire serial i/o transmission mode as communication mode sio2md2 = 0, sio2md1 = 0 <3> enabling communication operation (sio2csie = 1 ) (a) to output internal clock from shift clock (sio2md0 = 1 ) output the internal clock. (b) to input external clock as shift clock (sio2md0 = 0 ) input the external clock. <1> setting of pin <2> setting of 3-wire serial i/o mode <3> enables communication operation <4> setting of interrupt <5> writing to sio2sfr, starting transmission operation end of transmission (irqsio2 = 1) <6> interrupt routine yes no
231 pd17717, 17718, 17719 data sheet u12330ej2v0ds <4> setting of interrupt execute the ei instruction and set the ipsio2 flag to 1 . <5> setting of transmit data to sio2sfr (put sio2sfr) the 3-wire serial i/o transmission operation is started as soon as data has been set, and the 8-bit transmit data is output from the so2 pin. <6> interrupt routine when the 3-wire serial i/o transmission operation has been completed, the interrupt request flag irqsio2 is issued. when the interrupt is accepted, execution branches to the vector address. caution transfer is not started even if the sio2csie flag is set to 1 after data has been written to sio2sfr.
232 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.2.7 sbi mode in the sbi (serial bus interface) mode, an address to select a target device for serial communication, a command that gives the selected device an instruction, and actual data can be output to the serial data bus. therefore, a signal line for handshaking, which is necessary for connecting two or more devices with the conventional clocked serial interface, is not necessary. (1) outline of sbi mode in the sbi mode, communication is performed by using the sck and sb0 (or sb1) pins. table 16-4 shows the outline of the sbi mode. table 16-4. outline of sbi mode pin used for communication sck pin (serial clock i/o pin) sb0 (sb1) pin (serial data i/o pin) transmission/reception transmit data sequentially output from msb of shift register to data i/o pin in operation synchronization with falling of sck pin receive data value of data i/o pin is sequentially input from lsb of shift register in synchronization with rising of sck pin. transmission/reception master transmission/reception is started by setting transfer data to shift start register after sbi mode has been set. slave waits for clock from master with sck pin going into high-impedance state after sbi mode has been set. interrupt issues interrupt request irqsio2 at rising edge of 9th count of clock. clock pin master outputs more than 10 counts and uses 9th count and those that follow for acknowledge. used to control busy after acknowledge has been detected. clock line goes high after releasing of busy has been detected. slave goes into high-impedance state.
233 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.2.8 sbi mode operation sbi is a high-speed serial interface in compliance with the nec serial bus format. sbi uses a single master device and employs the clocked serial i/o format with the addition of a bus configuration function. this function enables devices to communicate using only two lines. thus, when making up a serial bus with two or more microcontrollers and peripheral ics, the number of ports to be used and the number of wires on the board can be decreased. the master device outputs three kinds of data to slave devices on the serial data bus: ?ddresses?to select a device to be communicated with, ?ommands?to instruct the selected device, and ?ata?which is actually required. the slave device can identify the received data into ?ddress? ?ommand? or ?ata? by hardware. this function enables the application program serial interface 2 control portions to be simplified. the sbi function is incorporated into various devices including 75x/xl-series devices and 78k-series and 17k-series of 8-bit and 16-bit single-chip microcontrollers. figure 16-15 shows a serial bus configuration example when a cpu having a serial interface compliant with sbi and peripheral ics are used. in sbi, the sb0 (sb1) serial data i/o pin is an open-drain output pin and therefore the serial data bus line behaves in the same way as the wired-or configuration. in addition, a pull-up resistor must be connected to the serial data bus line. when the sbi mode is used, refer to (9) sbi mode precautions (d) described later. figure 16-15. example of serial bus configuration with sbi caution when exchanging the master cpu/slave cpu, a pull-up resistor is necessary for the serial clock line (sck) as well because serial clock line (sck) input/output switching is carried out asynchronously between the master and slave cpus. master cpu sck sb0 (sb1) sck sb0 (sb1) sck sb0 (sb1) sck sb0 (sb1) slave cpu address 1 slave cpu address 2 slave ic address n serial clock serial data bus v dd
234 pd17717, 17718, 17719 data sheet u12330ej2v0ds (1) sbi functions in the conventional serial i/o format, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary, to provide chip select signal to identify command and data, and to judge the busy state, because only the data transfer function is available. if these operations are to be controlled by software, the software must be heavily loaded. in sbi, a serial bus can be configured with two signal lines of sck and sb0 (sb1). thus, use of sbi leads to reduction in the number of microcontroller ports and that of wirings and routings on the board. the sbi functions are described below. (a) address/command/data identify function serial data is distinguished into addresses, commands, and data. (b) chip select function by address transmission the master executes slave chip selection by address transmission. (c) wake-up function the slave can easily judge address reception (chip select judgment) with the wake-up function (which can be set/reset by software). when the wake-up function is set, the interrupt request signal (irqsio2) is generated upon reception of a match address. thus, when communication is executed with two or more devices, the cpu except the selected slave devices can operate regardless of underway serial communications. (d) acknowledge signal (ack) control function the acknowledge signal to check serial data reception is controlled. (e) busy signal (busy) control function the busy signal to report the slave busy state is controlled.
235 pd17717, 17718, 17719 data sheet u12330ej2v0ds (2) sbi definition the sbi serial data format and the signals to be used are defined as follows. serial data to be transferred with sbi consists of three kinds of data: address , command , and data . figure 16-16 shows the address, command, and data transfer timings. figure 16-16. sbi transfer timings remark the dotted line indicates ready status. the bus release signal and the command signal are output by the master device. busy is output by the slave signal. ack can be output by either the master or slave device (normally, the 8-bit data receiver outputs). serial clocks continue to be output by the master device from 8-bit data transfer start to busy reset. sck sb0 (sb1) sck sb0 (sb1) sck sb0 (sb1) 89 9 a7 a0 ack busy c7 c0 ack busy ready 89 d7 d0 ack busy ready address transfer command transfer data transfer bus release signal command signal
236 pd17717, 17718, 17719 data sheet u12330ej2v0ds (a) bus release signal (rel) the bus release signal is a signal with the sb0 (sb1) line which has changed from the low level to the high level when the sck line is at the high level (without serial clock output). this signal is output by the master device. figure 16-17. bus release signal the bus release signal indicates that the master device is going to transmit an address to the slave device. the slave device incorporates hardware to detect the bus release signal. (b) command signal (cmd) the command signal is a signal with the sb0 (sb1) line which has changed from the high level to the low level when the sck line is at the high level (without serial clock output). this signal is output by the master device. figure 16-18. command signal the slave device incorporates hardware to detect the command signal. sck "h" sb0 (sb1) sck "h" sb0 (sb1)
237 pd17717, 17718, 17719 data sheet u12330ej2v0ds (c) address an address is 8-bit data which the master device outputs to the slave device connected to the bus line in order to select a particular slave device. figure 16-19. addresses 8-bit data following bus release and command signals is defined as an address . in the slave device, this condition is detected by hardware and whether or not 8-bit data matches the own specification number (slave address) is checked by hardware. if the 8-bit data matches the slave address, the slave device has been selected. after that, communication with the master device continues until a release instruction is received from the master device. figure 16-20. slave selection with address sck a7 a6 a5 a4 a3 a2 a1 a0 12345678 sb0 (sb1) address command signal bus release signal master slave 1 not selected slave 2 selected slave 3 not selected slave 4 not selected slave 2 address transmission
238 pd17717, 17718, 17719 data sheet u12330ej2v0ds (d) command and data the master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. figure 16-21. commands figure 16-22. data 8-bit data following a command signal is defined as command data. 8-bit data without command signal is defined as data . command and data operation procedures are allowed to determine by user according to communications specifications. sck d7 d6 d5 d4 d3 d2 d1 d0 12345678 sb0 (sb1) data sck c7 c6 c5 c4 c3 c2 c1 c0 12345678 sb0 (sb1) command command signal
239 pd17717, 17718, 17719 data sheet u12330ej2v0ds (e) acknowledge signal (ack) the acknowledge signal is used to check serial data reception between transmitter and receiver. figure 16-23. acknowledge signal [when output in synchronization with 11th clock sck] [when output in synchronization with 9th clock sck] remark the dotted line indicates ready status. the acknowledge signal is one-shot pulse to be generated at the falling edge of sck after 8-bit data transfer. it can be positioned anywhere and can be synchronized with any clock sck. after 8-bit data transmission, the transmitter checks whether the receiver has returned the acknowledge signal. if the acknowledge signal is not returned for the preset period of time after data transmission, it can be judged that data reception has not been carried out correctly. sck sb0 (sb1) 8 9 10 11 ack 89 ack sck sb0 (sb1)
240 pd17717, 17718, 17719 data sheet u12330ej2v0ds (f) busy signal (busy) and ready signal (ready) the busy signal is intended to report to the master device that the slave device is preparing for data transmission/reception. the ready signal is intended to report to the master device that the slave device is ready for data transmission/reception. figure 16-24. busy and ready signals in sbi, the slave device notifies the master device of the busy state by setting sb0 (sb1) line to the low level. the busy signal output follows the acknowledge signal output from the master or slave device. it is set/ reset at the falling edge of sck. when the busy signal is reset, the master device automatically terminates the output of sck serial clock. when the busy signal is reset and the ready signal is set, the master device can start the next transfer. ready ack sck sb0 (sb1) busy 89
241 pd17717, 17718, 17719 data sheet u12330ej2v0ds (3) various signals in sbi mode figures 16-25 to 16-30 show various signals and each flag operation of serial i/o2sbi registers 0 and 1 in sbi. table 16-5 lists various signals in sbi. figure 16-25. sio2relt, sio2cmdt, sio2reld, and sio2cmdd operations (master) figure 16-26. sio2relt and sio2cmdd operations (slave) sck sb0 (sb1) sio2relt sio2cmdt sio2cmdd sio2reld sio2sfr slave address write to sio2sfr (transfer start instruction) write ffh to sio2sfr (transfer start instruction) sio2sfr sck sb0 (sb1) sio2reld sio2cmdd transfer start instruction a7 a6 a1 a0 12 789 ready a7 a6 a1 a0 ack slave address when addresses coincides when addresses do not coincide
242 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 16-27. sio2ackt operation caution do not set sio2ackt before completion of transfer. sck 6 sb0 (sb1) sio2ackt 7 8 9 d2 d1 d0 ack when set during this period ack signal is output for a period of one clock just after setting
243 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 16-28. sio2acke operations (a) when sio2acke = 1 upon completion of transfer (b) when set after completion of transfer (c) when sio2acke = 0 upon completion of transfer (d) when ?io2acke = 1 period is short sb0 (sb1) sio2acke 7 89 d1 d0 ack 6 d2 if set during this period and sio2acke = 1 at the fallin g ed g e of the next sck ack signal is output for a period of one clock just after setting sck sb0 (sb1) sio2acke if set and cleared during this period and sio2acke = 0 at the falling edge of sck ack signal is not output d2 d1 d0 sck sb0 (sb1) sio2acke 1 2 789 d7 d6 d2 d1 d0 ack when sio2acke = 1 at this point ack signal is output at 9th clock sck sb0 (sb1) sio2acke 1 2 789 d7 d6 d2 d1 d0 when sio2acke = 0 at this point ack signal is not output sck
244 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 16-29. sio2ackd operations (a) when ack signal is output at 9th clock of sck (b) when ack signal is output after 9th clock of sck (c) clear timing when transfer start is instructed in busy figure 16-30. sio2bsye operation sck sb0 (sb1) sio2ackd 789 d1 d0 ack 6 d2 transfer start instruction sio2sfr transfer start sb0 (sb1) sio2ackd ack 9 sio2sfr 78 d1 6 d2 d0 transfer start instruction transfer start sck sck sb0 (sb1) sio2ackd ack 9 transfer start instruction sio2sfr 78 d1 6 d2 d0 d6 d7 busy sck sb0 (sb1) sio2 bsye 7 89 ack 6 when sio2 bsye = 1 at this point busy if reset during this period and sio2 bsye = 0 at the falling edge of sck d2 d1 d0
245 pd17717, 17718, 17719 data sheet u12330ej2v0ds table 16-5. various signals in sbi mode (1/2) timing chart definition signal name output device output condition effects on flag meaning of signal cmd signal is output to indicate that transmit data is an address. i) transmit data is an address after rel signal output. ii) rel signal is not output and trans- mit data is an command. low-level signal to be output to sb0 (sb1) during one-clock period of sck after completion of serial reception [synchronous busy signal] low-level signal to be output to sb0 (sb1) following acknowledge signal <1> sio2bsye = 0 <2> execution of instruction for data write to sio2sfr (transfer start instruction) <3> address signal reception master/ slave sb0 (sb1) rising edge when sck = 1 master bus release signal (rel) sio2relt set sio2reld set sio2cmdd clear sio2cmdd set sio2cmdt set master command signal (cmd) sb0 (sb1) falling edge when sck = 1 acknowledge signal (ack) <1> sio2acke = 1 <2> sio2ackt set sio2ackd set completion of reception slave busy signal (busy) sio2bsye = 1 serial receive disable because of processing serial receive enable slave ready signal (ready) high-level signal to be output to sb0 (sb1) before serial transfer start and after completion of serial transfer [synchronous busy output] sck d0 ready sb0 (sb1) d0 ready sb0 (sb1) ack busy busy ack 9 sck "h" sb0 (sb1) "h" sb0 (sb1) sck
246 pd17717, 17718, 17719 data sheet u12330ej2v0ds timing chart definition signal name output device output condition effects on flag meaning of signal synchronous clock to output address/command/ data, ack signal, synchro- nous busy signal, etc. address/command/data are transferred with the first eight synchronous clocks. 8-bit data to be transferred in synchronization with sck after output of only cmd signal without rel signal output master numeric values to be processed with slave or master device serial clock (sck) timing of signal output to serial data bus address value of slave device on the serial bus address (a7 to a0) 8-bit data to be transferred in synchronization with sck after output of rel and cmd signals master commands (c7 to c0) instructions and messages to the slave device master/ slave data (d7 to d0) 8-bit data to be transferred in synchronization with sck without output of rel and cmd signals table 16-5. various signals in sbi mode (2/2) when sio2csie = 1, execution of instruction for data write to sio2sfr (serial transfer start instruction) note 2 notes 1. when sio2wup = 0, csiif0 is set at the rising edge of the 9th clock of sck. when sio2wup = 1, an address is received. only when the address coincides the serial i/o2 slave address register (sio2sva) val ue, irqsio2 is set. (if the address does not coincide with the value of sio2sva, sio2reld is cleared). 2. in busy state, transfer starts after the ready state is set. master sio2sfr set (rising edge of 9th clock of sck) note 1 sck sb0 (sb1) 1278910 sck sb0 (sb1) 1278 rel cmd sck sb0 (sb1) 1278 cmd sck sb0 (sb1) 1278
247 pd17717, 17718, 17719 data sheet u12330ej2v0ds (4) pin configuration the serial clock pin sck and serial data i/o pin sb0 (sb1) have the following configurations. (a) sck ............... serial clock input/output pin <1> master ... cmos and push-pull output <2> slave ..... schmitt input (b) sb0 (sb1) ..... serial data input/output dual-function pin both master and slave devices have an n-ch open drain output and a schmitt input. because the serial data bus line has an n-ch open-drain output, an external pull-up resistor is necessary. figure 16-31. pin configuration caution because the n-ch open-drain must be turned off at time of data reception, write ffh to presettable shift register 2 (sio2sfr) in advance. the n-ch open-drain can be turned off at any time of transfer. however, when the wake-up function specification bit (sio2wup) = 1, the n-ch transistor is always turned off. thus, it is not necessary to write ffh to sio2sfr. data input data output data input data output (clock input) clock output master device clock input (clock output) serial clock sck sck r l serial data bus sb0 (sb1) sb0 (sb1) n-ch open-drain n-ch open-drain slave device
248 pd17717, 17718, 17719 data sheet u12330ej2v0ds (5) address coincidence detection method in the sbi mode, the master transmits a slave address to select a specific slave device. coincidence of the addresses can be automatically detected by hardware. irqsio2 is set only when the slave address transmitted by the master coincides with the address set to sio2sva when the wake-up function specification bit (sio2wup) = 1. if the sio2sic of the serial i/o2 interrupt timing specification register 0 is set, the wake-up function cannot be used even if sio2wup is set (an interrupt request signal is generated when bus release is detected). to use the wake-up function, clear sio2sic to 0. cautions 1. slave selection/non-selection is detected by the coincidence of the slave address received after bus release (sio2reld = 1). for this coincidence detection, the coincidence detection interrupt (intcsi0) of the address to be generated with sio2wup = 1 is normally used. thus, execute selection/non-selection detection by slave address when sio2wup = 1. 2. when detecting selection/non-selection without the use of interrupt with sio2wup = 0, do so by means of transmission/reception of the command preset by program instead of using the address coincidence detection method. (6) error detection in the sbi mode, the serial data bus sb0 (sb1) status being transmitted is fetched into the destination device, that is, the presettable shift register 2 (sio2sfr). thus, transmit errors can be detected in the following way. (a) method of comparing sio2sfr data before transmission to that after transmission in this case, if two data differ from each other, a transmit error is judged to have occurred. (b) method of using the serial i/o2 slave address register (sio2sva) transmit data is set to both sio2sfr and sio2sva and is transmitted. after termination of transmission, sio2coi flag (coincidence signal coming from the address comparator) of the serial i/o2 operating mode register 0 is tested. if 1 , normal transmission is judged to have been carried out. if 0 , a transmit error is judged to have occurred. (7) communication operation in the sbi mode, the master device selects normally one slave device as communication target from among two or more devices by outputting an address to the serial bus. after the communication target device has been determined, commands and data are transmitted/received and serial communication is realized between the master and slave devices. figures 16-32 to 16-35 show data communication timing charts. shift operation of the presettable shift register 2 (siosfr) is carried out at the falling edge of serial clock (sck). transmit data is output with msb set as the first bit from the sb0/p2d0 or sb1/p2d1 pin. receive data input to the sb0 (or sb1) pin at the rising edge of sck is latched into the sio2sfr.
249 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 16-32. address transmission from master device to slave device (sio2wup = 1) 1 2 3 4 5 6 7 8 9 sck pin a7 a6 a5 a4 a3 a2 a1 a0 ack busy sb0 (sb1) pin software operation serial transmission irqsio2 generation sio2ackd set sck stop hardware operation sio2wup 0 sio2ackt set software operation sio2cmdd set irqsio2 generation ack output hardware operation sio2cmdt set sio2relt set sio2cmdt set write to sio2sfr interrupt service (preparation for the next serial transfer) master device operation (transmitter) transfer line slave device operation (receiver) sio2cmdd clear sio2cmdd set sio2reld set serial reception busy output ready (when sio2sva = sio2sfr) address busy clear busy clear
250 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 16-33. command transmission from master device to slave device 1 2 3 4 5 6 7 8 9 sck pin c7 c6 c5 c4 c3 c2 c1 c0 ack busy sb0 (sb1) pin software operation serial transmission irqsio2 generation sio2ackd set sck stop hardware operation sio2ackt set software operation irqsio2 generation ack output hardware operation sio2cmdt set write to sio interrupt service (preparation for the next serial transfer) master device operation (transmitter) transfer line slave device operation (receiver) sio2cmdd set serial reception busy output ready command busy clear busy clear sio2sfr read command analysis
251 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 16-34. data transmission from master device to slave device 1 2 3 4 5 6 7 8 9 sck pin d7 d6 d5 d4 d3 d2 d1 d0 ack busy sb0 (sb1) pin software operation serial transmission irqsio2 generation sio2ackd set sck stop hardware operation sio2ackt set software operation irqsio2 generation ack output hardware operation write to sio2sfr interrupt service (preparation for the next serial transfer) master device operation (transmitter) transfer line slave device operation (receiver) serial reception busy output ready data busy clear busy clear sio2sfr read
252 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 16-35. data transmission from slave device to master de vice 1 2 3 4 5 6 7 8 9 sck pin d7 d6 d5 d4 d3 d2 d1 d0 ack busy sb0 (sb1) pin software operation serial reception irqsio2 generation ack output serial reception hardware operation software operation irqsio2 generation sio2ackd set hardware operation ffh write to sio2sfr master device operation (receiver) transfer line slave device operation (transmitter) serial transmission busy output ready data busy clear write to sio2sfr sck stop busy clear 12 ready busy d7 d6 sio2ackt set sio2sfr read receive data processing ffh write to sio2sfr write to sio2sfr
253 pd17717, 17718, 17719 data sheet u12330ej2v0ds (8) transfer start serial transfer is started by setting transfer data to the presettable shift register 2 (sio2sfr) when the following two conditions are satisfied. serial interface 2 operation control flag (sio2csie) = 1 internal serial clock is stopped or sck is at high level after 8-bit serial transfer. cautions 1. if sio2csie is set to ??after data write to sio2sfr, transfer does not start. 2. because the n-ch transistor must be turned off for data reception, write ffh to sio0 in advance. however, when the make-up function control flag (sio2wup) = 1, the n-ch transistor is always turned off. thus, it is not necessary to write ffh to sio2sfr. 3. if data is written to sio2sfr when the slave is busy, the data is not lost. when the busy state is cleared and sb0 (or sb1) input is set to the high level (ready) state, transfer starts. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (irqsio2) is set.
254 pd17717, 17718, 17719 data sheet u12330ej2v0ds (9) sbi mode precautions (a) slave selection/non-selection is detected by coincidence detection of the slave address received after bus release (sio2reld = 1). for this coincidence detection, match interrupt (irqsio2) of the address to be generated with sio2wup = 1 is normally used. thus, execute selection/non-selection detection by slave address when sio2wup = 1. (b) when detecting selection/non-selection without the use of interrupt with sio2wup = 0, do so by means of transmission/reception of the command preset by program instead of using the address coincidence detection method. (c) if sio2wup is set to 1 during busy signal output, busy is not cleared. in sbi, the busy signal continues to be output after busy clear instruction generation to the falling edge of the next serial clock (sck). before setting sio2wup to 1, be sure to clear busy and then check that the sb0 (sb1) has become high- level. (d) for pins which are to be used for data input/output, be sure to carry out the following settings before serial transfer of the 1st byte after reset input. <1> set the p2d0 and p2d1 latches to 1. <2> set the sio2relt flag of serial i/o2sbi register 1 to 1. <3> reset the p2d0 and p2d1 output latches from 1 to 0. (e) when device is in the master mode, follow the procedure below to judge whether slave device is in the busy state or not. <1> detect acknowledge signal (ack) or interrupt request signal generation. <2> set the port 2d bit i/o selection register p2dbio0 (or p2dbio1) of the sb0/p2d0 (or sb1/p2d1) pin into the input mode. <3> read out the pin state (when the pin level is high, the ready state is set). after the detection of the ready state, set the p2dbio0 (or p2dbio1) to 1 and return to the output mode.
255 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.2.9 2-wire serial i/o mode the 2-wire serial i/o mode is validated when sio2md1 and 2 of the serial i/o2 operation mode register are set to 1 and sio2wat1 of the serial interface 2 interrupt timing specification register is cleared to 0. (1) outline of 2-wire serial i/o mode in the 2-wire serial i/o mode, the scl and sda pins are used for communication. table 16-6 shows the outline of the 2-wire serial i/o mode. table 16-6. outline of 2-wire serial i/o mode pin used for communication scl pin (serial clock i/o pin) sda pin (serial data i/o pin) transmission/reception transmit data sequentially output from msb of shift register to data i/o pin in operation synchronization with falling of scl pin receive data value of data i/o pin is sequentially input from lsb of shift register in synchronization with rising of scl pin. transmission/reception master transmission/reception is started by setting transfer data to shift start register after 2-wire serial i/o master mode has been set. slave waits for clock from master with scl pin going into high-impedance state after 2-wire serial i/o slave mode has been set. interrupt issues interrupt request irqsio2 at rising edge of 8th count of clock. clock pin master stops output of scl pin at rising edge of 8th count and retains high level until next transmission/reception operation is started slave goes into high-impedance state in 2-wire serial i/o slave mode. caution the sio2cmdt and sio2relt flags of the serial i/o2sbi register 1 are disabled from being used when the 2-wire serial i/o mode is used. figure 16-36. serial bus configuration example in 2-wire serial i/o mode scl sda master slave scl sda v dd v dd
256 pd17717, 17718, 17719 data sheet u12330ej2v0ds (2) timing chart figure 16-37 shows the timing chart in the 2-wire serial i/o mode. figure 16-37. timing chart in 2-wire serial i/o mode the sda pin is an n-ch open-drain i/o pin and must be externally pulled up. because the n-ch transistor must be turned off when data is received, write ffh to sio2sfr in advance. (3) starting transfer serial transfer is started by setting data to the presettable shift register 2 (sio2sfr) when the following two conditions are satisfied. control flag of operation of serial interface 2 (sio2csie) = 1 when internal serial clock is stopped or scl is low after 8-bit serial transfer serial transfer is automatically stopped and the interrupt request flag (irqsio2) is set after completion of 8- bit transfer. (4) detection of error because the status of the serial bus sda during transmission is also input to sio2sfr of the device that is transmitting data in the 2-wire serial i/o mode, a transmission error, if any, can be detected as follows: (a) by comparing sio2sfr data before and after transmission in this case, it is assumed that a transmission error has occurred if the two data differ. (b) by using serial interface 2 slave address register (sio2sva) the transmit data is set to sio2sfr and sio2sva and transmission is executed. after completion of transmission, the sio2coi flag of the serial i/o2 operation mode register 0 (coincidence signal from the address comparator) is tested. if the flag is 1 , communication has been executed normally; if it is 0 , it is assumed that a transmission error has occurred. 12345678 d7 d6 d5 d4 d3 d2 d1 d0 starts transfer in synchronization with falling of scl end of transfer irqsio2 flag scl pin sda pin writing to shift register
257 pd17717, 17718, 17719 data sheet u12330ej2v0ds (5) program flowchart in 2-wire serial i/o mode a program flowchart example in the 2-wire serial i/o transmission mode is shown below. figure 16-38. example flowchart in 2-wire serial i/o transmission mode remark to execute a 2-wire serial i/o operation with the same setting as before, start from step <5>. <1> setting of pin (a) setting of data pin in 2-wire serial i/o mode set the i/o control mode of the data pin to 1 (output), and the port latch of the data pin to 0 . (b) setting of shift clock in 2-wire serial i/o mode set the i/o control mode of the shift clock to 1 (output), and the port latch of the shift clock to 1 . <2> setting 2-wire serial i/o transmission mode as communication mode sio2md2 = 1, sio2md1 = 1 <3> enabling communication operation (sio2csie = ?? (a) to output internal clock from shift clock (sio2md0 = ?? output the internal clock. (b) to input external clock as shift clock (sio2md0 = ?? input the external clock. <1> setting of pin <2> setting of 2-wire serial i/o mode <3> enables communication operation <4> setting of interrupt end of transmission (irqsio2 = 1) <6> interrupt routine yes no <5> writing to sio2sfr
258 pd17717, 17718, 17719 data sheet u12330ej2v0ds <4> setting of interrupt execute the ei instruction and set the ipsio2 flag to 1 . <5> setting of transmit data to sio2sfr (put sio2sfr) the 2-wire serial i/o transmission operation is started as soon as data has been set, and the 8-bit transmit data is output from the sda pin. <6> interrupt routine when the 2-wire serial i/o transmission operation has been completed, the interrupt request flag irqsio2 is issued. when the interrupt is accepted, execution branches to the vector address. cautions 1. transfer is not started even if sio2csie is set to ??after data has been written to sio2sfr. 2. write ffh to sio2sfr in advance because the n-ch transistor must be turned off during data reception.
259 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.2.10 i 2 c bus mode the i 2 c bus mode becomes valid when sio2md1 and 2 of the serial i/o2 operation mode register 1 are set to 1 and sio2wat1 of the serial i/o2 interrupt timing specification register 1 is set to 1. in the i 2 c transmission mode, clear the sio2bsye flag to 0 . in the i 2 c reception mode, set the sio2bsye flag to 1 . the functions that can be used in the i2c bus mode of the upd17717, 17718, and 17719 are listed below. table 16-7. functions in i 2 c bus mode of pd17717, 17718, and 17719 operation mode supported by serial interface 2 multi-master software-supported single master hardware-supported basic transmission/reception acknowledge control wait control slave hardware-supported wait request wake-up function (1) outline of i 2 c bus mode in the i 2 c bus mode, communication is performed by using the scl and sda pins. table 16-8 shows the outline of the i 2 c bus mode. table 16-8. outline of i 2 c bus mode pins used for transmission scl pin (serial clock i/o pin) sda pin (serial data i/o pin) transmission/reception transmit data sequentially output from msb of shift register to data i/o pin in operation synchronization with falling of scl pin. receive data value of data i/o pin is input from lsb of shift register in synchronization with rising of scl pin. transmission/reception master transmission/reception is started by setting transfer data to shift start register after i 2 c master mode has been set. slave waits for clock from master with scl pin going into high-impedance state after i 2 c slave mode has been set. interrupt issues interrupt request irqsio2 at rising of clock of 8th count. clock pin master 9th count and those that follow are used for acknowledge. slave goes into high-impedance state.
260 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.2.11 i 2 c bus mode operation the i 2 c bus mode is provided for when communication operations are performed between a single master device and multiple slave devices. this mode configures a serial bus that includes only a single master device, and is based on the clocked serial i/o format with the addition of bus configuration functions, which allows the master device to communicate with a number of (slave) devices using only two lines: scl and sda. consequently, when the user plans to configure a serial bus which includes multiple microcontrollers and peripheral devices, using this configuration results in reduction of the required number of port pins and on-board wires. in the i 2 c bus specification, the master sends start condition, data, and stop condition signals to slave devices through the serial data bus, while slave devices automatically detect and distinguish the type of signals due to the signal detection function incorporated as hardware. this simplifies i 2 c bus control sections in the application program. an example of a serial bus configuration is shown in figure 16-39. this system below is composed of cpus and peripheral ics having serial interface hardware that complies with the i 2 c bus specification. note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because open-drain buffers are used for the serial clock pin (scl) and the serial data i/o pin (sda) on the i 2 c bus. the signals used in the i 2 c bus mode are described in table 16-9. figure 16-39. example of serial bus configuration using i 2 c bus scl sda scl sda scl sda scl sda slave ic slave cpu2 slave cpu1 master cpu v dd serial clock serial data bus v dd
261 pd17717, 17718, 17719 data sheet u12330ej2v0ds (1) i 2 c bus mode functions in the i 2 c bus mode, the following functions are available. (a) automatic identification of serial data slave devices automatically detect and identifies start condition, data, and stop condition signals sent in series through the serial data bus. (b) chip selection by specifying device addresses the master device can select a specific slave device connected to the i 2 c bus and communicate with it by sending in advance the address data corresponding to the destination device. (c) wake-up function when address data is sent from the master device, slave devices compare it with the value registered in their serial i/o2 slave address registers (sio2sva). if the values in one of the slave devices coincide, the slave device generates an interrupt signal (the interrupt also occurs when the stop condition is detected). therefore, cpus other than the selected slave device on the i 2 c bus can perform independent operations during the serial communication. (d) acknowledge signal (ack) control function the master device and a slave device send and receive acknowledge signals to confirm that the serial communication has been executed normally. (e) wait signal (wait) control function the slave device outputs a wait signal on the bus to inform the master device of the wait status. (2) i 2 c bus definition this section describes the format of serial data communications and functions of the signals used in the i 2 c bus mode. first, the transfer timings of the start condition, data, and stop condition signals, which are output onto the signal data bus of the i 2 c bus, are shown in figure 16-40. figure 16-40. i 2 c bus serial data transfer timing the start condition, slave address, and stop condition signals are output by the master. the acknowledge signal (ack) is output by either the master or the slave device (normally by the device which has received the 8-bit data that was sent). a serial clock (scl) is continuously supplied from the master device. 1-7 8 9 1-7 8 9 1-7 8 9 address r/w ack data ack data ack scl start condition sda stop condition
262 pd17717, 17718, 17719 data sheet u12330ej2v0ds (a) start condition when the sda pin level is changed from high to low while the scl pin is high, this transition is recognized as the start condition signal. this start condition signal, which is created using the scl and sda pins, is output from the master device to slave devices to initiate a serial transfer. refer to 16.2.12 cautions on using i 2 c bus mode for details of the start condition output. the start condition signal is detected by hardware incorporated in slave devices. figure 16-41. start condition (b) address the 7 bits following the start condition signal are defined as an address. the 7-bit address data is output by the master device to specify a specific slave from among those connected to the bus line. each slave device on the bus line must therefore have a different address. therefore, after a slave device detects the start condition, it compares the 7-bit address data received and the data of the serial i/o2 slave address register (sio2sva). after the comparison, only the slave device in which the data are a match becomes the communication partner, and subsequently performs communication with the master device until the master device sends a start condition or stop condition signal. figure 16-42. address (c) transfer direction specification the 1 bit that follows the 7-bit address data will be sent from the master device, and it is defined as the transfer direction specification bit. if this bit is 0, it is the master device which will send data to the slave. if it is 1, it is the slave device which will send data to the master. figure 16-43. transfer direction specification h scl sda 1234567 a6 a5 a4 a3 a2 a1 a0 r/w address scl sda 234567 a6 a5 a4 a3 a2 a1 a0 r/w transfer direction specification scl 8 1 sda
263 pd17717, 17718, 17719 data sheet u12330ej2v0ds (d) acknowledge signal (ack) the acknowledge signal indicates that the transferred serial data has definitely been received. this signal is used between the sending side and receiving side devices for confirmation of correct data transfer. in principle, the receiving side device returns an acknowledge signal to the sending device each time it receives 8-bit data. the only exception is when the receiving side is the master device and the 8-bit data is the last transfer data; the master device outputs no acknowledge signal in this case. the sending side that has tranferred 8-bit data waits for the acknowledge signal which will be sent from the receiving side. if the sending side device receives the acknowledge signal, which means a successful data transfer, it proceeds to the next processing. if this signal is not sent back from the slave device, this means that the data sent has not been received by the slave device, and therefore the master device outputs a stop condition signal to terminate subsequent transmissions. figure 16-44. acknowledge signal (e) stop condition if the sda pin level changes from low to high while the scl pin is high, this transition is defined as a stop condition signal. the stop condition signal is output from the master to the slave device to terminate a serial transfer. the stop condition signal is detected by hardware incorporated in the slave device. figure 16-45. stop condition 1234567 a6 a5 a4 a3 a2 a1 a0 r/w scl sda 9 8 ack h scl sda
264 pd17717, 17718, 17719 data sheet u12330ej2v0ds (f) wait signal (wait) the wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data. during the wait state, the slave device continues to output the wait signal by keeping the scl pin low to delay subsequent transfers. when the wait state is released, the master device can start the next transfer. for the releasing operation of slave devices, refer to 16.2.12 cautions on using i 2 c bus mode . figure 16-46. wait signal (a) wait of 8 clock cycles (b) wait of 9 clock cycles scl of master device d2 d1 d0 ack d7 output by manipulating sio2ackt 6789 1 3 24 d6 d5 d4 set low because slave device drives low, though master device returns to hi-z state. no wait is inserted after 9th clock cycle. (and before master device starts next transfer.) scl of slave device scl sda scl of master device set low because slave device drives low, though master device returns to hi-z state. scl of slave device scl d2 d1 d0 ack d7 output based on the value set in sio2acke in advance 6789 23 d6 d5 1 sda
265 pd17717, 17718, 17719 data sheet u12330ej2v0ds (3) various signals in i 2 c bus mode a list of signals in the i 2 c bus mode is given in table 16-9. table 16-9. signals in i 2 c bus mode signal name output definition output condition affected flag(s) signal function device start condition master sda falling edge when sio2cmdt is sio2cmdd is indicates that sequent scl is high note 1 set. set. transmission data are address data and serial communication starts. stop condition master sda rising edge when sio2relt is set. sio2reld is set. indicates end of serial scl is high note 1 sio2cmdd is cleared. transmission. acknowledge master or low-level signal of sda sio2acke = 1 sio2ackd is set. indicates completion of signal (ack) slave output during one scl sio2ackt is reception of 1 byte. clock cycle after serial set. reception wait (wait) slave low-level signal output sio2wat1, indicates state in which to scl sio2wat0 = 1x. serial reception is not possible. serial clock master synchronization clock for irqsio2 is serial communication (scl) output of various signals set. note 3 synchronization signal. address master 7-bit data output in indicates address value (a6 to a0) synchronization with scl for specification of slave after start condition output on serial bus. transfer direction master 1-bit data output in indicates whether data (r/w) synchronization with scl transmission or reception after address output is to be performed. data master or 8-bit data output in indicates data actually to (d7 to d0) slave synchronization with be sent. scl, not immediately after start condition output notes 1. the level of the serial clock can be controlled by sio2clc of serial i/o2 interrupt timing specification register 1. 2. in the wait state, the serial transfer operation will be started after the wait state is released. 3. if the 8-clock wait is selected when sio2wup = 0, irqsio2 is set at the rising edge of the 8th clock cycle of scl. if the 9-clock wait is selected when sio2wup = 0, irqsio2 is set at the rising edge of the 9th clock cycle of scl. irqsio2 is set if an address is received and that address coincides with the value of the serial i/o2 slave address register (sio2sva) when sio2wup = 1, or if the stop condition is detected. execution of instruction for data write to sio2sfr when sio2csie = 1 (serial transfer start instruction). note 2
266 pd17717, 17718, 17719 data sheet u12330ej2v0ds (4) pin configurations the configurations of the serial clock pin scl and the serial data i/o pins sda are shown below. (a) scl pin for serial clock input/output dual-function pin. <1> master ... n-ch open-drain output <2> slave ..... schmitt input (b) sda serial data input/output dual-function pin. uses n-ch open-drain output and schmitt-input buffers for both master and slave devices. note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because open-drain buffers are used for the serial clock pin (scl) and the serial data bus pin (sda0 or sda1) on the i 2 c bus. figure 16-47. pin configuration caution to receive data, the n-ch open-drain output must be in high-impedance state. therefore, set the sio2bsye flag of serial i/o2sbi register 0 to 1 in advance, and write ffh to the presettable shift register 2 (sio2sfr). when the wake-up function is used (by setting the sio2wup flag of the serial i/o2 operating mode register 1, however, do not write ffh to sio2sfr before reception. even if ffh is not written to sio2sfr, the n-ch open-drain output is always in high- impedance state. (5) address coincidence detection method in the i 2 c mode, the master can select a specific slave device by sending slave address data. irqsio2 is set if the slave address transmitted by the master coincides with the value set to the serial i/o2 slave address register (sio2sva) when a slave device address has a serial i/o2 slave address register (sio2sva), and the sio2wup flag is 1 (irqsio2 is also set when the stop condition is detected). when using the wake-up function, set sio2sic to 1. caution slave selection/non-selection is detected by the coincidence of the data (address) received after the start condition. for this coincidence detection, the coincidence detection interrupt (irqsio2) of the address to be generated with sio2wup = 1 is normally used. thus, execute selection/ non-selection detection by slave address when sio2wup = 1. v dd v dd scl sda master device clock output (clock input) data output data input slave devices (clock output) clock input data output data input scl sda
267 pd17717, 17718, 17719 data sheet u12330ej2v0ds (6) error detection in the i 2 c bus mode, transmission error detection can be performed by the following methods because the serial data bus sda status during transmission is also taken into the presettable shift register 2 (sio2sfr) of the transmitting device. (a) comparison of sio2sfr data before and after transmission in this case, a transmission error is judged to have occurred if the two data values are different. (b) using the serial i/o2 slave address register (sio2sva) transmit data is set in sio2sfr and sio2sva before transmission is performed. after transmission, the sio2coi bit (coincidence signal from the address comparator) of serial i/o2 operation mode register 0 is tested: "1" indicates normal transmission, and "0" indicates a transmission error. (7) communication operation in the i 2 c bus mode, the master selects the slave device to be communicated with from among multiple devices by outputting address data onto the serial bus. after the slave address data, the master sends the r/w bit which indicates the data transfer direction, and starts serial communication with the selected slave device. data communication timing charts are shown in figures 16-48 and 16-49 . in the transmitting device, the presettable shift register 2 (sio2sfr) shifts transmission data to the so latch in synchronization with the falling edge of the serial clock (scl), the so0 latch outputs the data on an msb- first basis from the sda pin to the receiving device. in the receiving device, the data input from the sda pin is taken into the sio2sfr in synchronization with the rising edge of scl.
268 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 16-48. data transmission from master to slave (both master and slave selected 9-clock wait) (1 of 3) (a) start condition to address l l l 1 a5 a4 a3 a2 a1 a0 w ack a6 2345678 d7 d6 d5 d4 d3 12345 9 l l l l l sio2sfr address master device operation transfer line slave device operation sio2sfr data h l l l l l l l h h h h sio2sfr ffh write sio2sfr sio2coi sio2ackd sio2cmdd sio2reld sio2cld p0a2 scl sda sio2wup sio2bsye sio2acke sio2cmdt sio2relt sio2clc sio2wrel sio2sic irqsio2 write sio2sfr sio2coi sio2ackd sio2cmdd sio2reld sio2cld p0a2 sio2wup sio2bsye sio2acke sio2cmdt sio2relt sio2clc sio2wrel sio2sic irqsio2 sio2csie sda p0abio3 p0abio2
269 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 16-48. data transmission from master to slave (both master and slave selected 9-clock wait) (2 of 3) (b) data l l l l 1 d5 d4 d3 d2 d1 d0 ack d6 d7 2345678 d7 d6 d5 d4 d3 12345 9 l l l l l l l sio2sfr address master device operation transfer line sio2sfr data h l l l l l l l h h h h sio2sfr ffh sio2sfr ffh write sio2sfr sio2coi sio2ackd sio2cmdd sio2reld sio2cld p0a2 scl sda sio2wup sio2bsye sio2acke sio2cmdt sio2relt sio2clc sio2wrel sio2sic irqsio2 write sio2sfr sio2coi sio2ackd sio2cmdd sio2reld sio2cld p0a2 sio2wup sio2bsye sio2acke sio2cmdt sio2relt sio2clc sio2wrel sio2sic irqsio2 sio2csie sda p0abio3 p0abio2 slave device operation
270 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 16-48. data transmission from master to slave (both master and slave selected 9-clock wait) (3 of 3) (c) stop condition l l 1 d5 d4 d3 d2 d1 d0 ack d6 d7 2345678 a6 a5 a4 a3 1234 9 l l l l sio2sfr data master device operation transfer line sio2sfr address h l l l l h h h sio2sfr ffh write sio2sfr sio2coi sio2ackd sio2cmdd sio2reld sio2cld p0a2 scl sda sio2wup sio2bsye sio2acke sio2cmdt sio2relt sio2clc sio2wrel sio2sic irqsio2 write sio2sfr sio2coi sio2ackd sio2cmdd sio2reld sio2cld p0a2 sio2wup sio2bsye sio2acke sio2cmdt sio2relt sio2clc sio2wrel sio2sic irqsio2 sio2csie sda p0abio3 p0abio2 slave device operation sio2sfr ffh
271 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 16-49. data transmission from slave to master (both master and slave selected 9-clock wait) (1 of 3) (a) start condition to address l l l 1 a0 a1 a2 a3 a4 a5 a6 r ack 2345678 d6 d7 d5 d4 d3 2 1345 9 l l l sio2sfr address master device operation transfer line sio2sfr ffh h l l l l l l l h h write sio2sfr sio2coi sio2ackd sio2cmdd sio2reld sio2cld p0a2 scl sda sio2wup sio2bsye sio2acke sio2cmdt sio2relt sio2clc sio2wrel sio2sic irqsio2 write sio2sfr sio2coi sio2ackd sio2cmdd sio2reld sio2cld p0a2 sio2wup sio2bsye sio2acke sio2cmdt sio2relt sio2clc sio2wrel sio2sic irqsio2 sio2csie sda p0abio3 p0abio2 slave device operation sio2sfr data
272 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 16-49. data transmission from slave to master (both master and slave selected 9-clock wait) (2 of 3) (b) data l l l l h h l 1 d1 d0 d2 d3 d4 d5 d6 d7 ack 2345678 d6 d7 d5 d4 d3 2 1345 9 l l l sio2sfr ffh master device operation transfer line sio2sfr ffh h l l l l l l l l l l h h write sio2sfr sio2coi sio2ackd sio2cmdd sio2reld sio2cld p0a2 scl sda sio2wup sio2bsye sio2acke sio2cmdt sio2relt sio2clc sio2wrel sio2sic irqsio2 write sio2sfr sio2coi sio2ackd sio2cmdd sio2reld sio2cld p0a2 sio2wup sio2bsye sio2acke sio2cmdt sio2relt sio2clc sio2wrel sio2sic irqsio2 sio2csie sda p0abio3 p0abio2 slave device operation sio2sfr data sio2sfr data
273 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 16-49. data transmission from slave to master (both master and slave selected 9-clock wait) (3 of 3) (c) stop condition l l 1 d1 d0 d2 d3 d4 d5 d6 d7 nak 2345678 a6 a5 a4 a3 1234 9 l l sio2sfr ffh master device operation transfer line sio2sfr address h l l l l l l h h write sio2sfr sio2coi sio2ackd sio2cmdd sio2reld sio2cld p0a2 scl sda sio2wup sio2bsye sio2acke sio2cmdt sio2relt sio2clc sio2wrel sio2sic irqsio2 write sio2sfr sio2coi sio2ackd sio2cmdd sio2reld sio2cld p0a2 sio2wup sio2bsye sio2acke sio2cmdt sio2relt sio2clc sio2wrel sio2sic irqsio2 sio2csie sda p0abio3 p0abio2 slave device operation sio2sfr data
274 pd17717, 17718, 17719 data sheet u12330ej2v0ds (8) start of transfer a serial transfer is started by setting transfer data in the presettable shift register 2 (sio2sfr) if the following two conditions have been satisfied: the serial interface 2 operation control flag (sio2csie) = 1. after an 8-bit serial transfer, the internal serial clock is stopped or scl is low. cautions 1. setting sio2csie to 1 after writing data in sio2sfr does not initiate transfer operation. 2. because the n-ch open-drain output must go into high-impedance during data reception, set the sio2bsye flag of serial i/o2sbi register 0 to 1 before writing ffh to sio2sfr. do not write ffh to sio2sfr before reception when the wake-up function is used (by setting the sio2wup flag of serial i/o2 operation mode register 1). even if ffh is not written to sio2sfr, the n-ch open-drain output is always high-impedance state. 3. if data is written to sio2sfr while the slave is in the wait state, that data is held. the transfer is started when scl is output after the wait state is released. when an 8-bit data transfer ends, serial transfer is stopped automatically and the interrupt request flag (irqsio2) is set. 16.2.12 cautions on using i 2 c bus mode (1) start condition output (master) the scl pin normally outputs a low-level signal when no serial clock is output. it is necessary to change the scl pin to high in order to output a start condition signal. set 1 in sio2clc of serial i/o2 interrupt timing specify register 1 to drive the scl pin high. after setting sio2clc, clear sio2clc to 0 and return the scl pin to low. if sio2clc remains 1, no serial clock is output. if it is the master device which outputs the start condition and stop condition signals, confirm that sio2cld is set to 1 after setting sio2clc to 1; a slave device may have set scl to low (wait state). figure 16-50. start condition output scl sio2clc sio2cmdt sio2cld sda
275 pd17717, 17718, 17719 data sheet u12330ej2v0ds (2) slave wait release (slave transmission) slave wait status is released by sio2wrel flag (bit 2 of serial i/o2 interrupt timing specification register 1) setting or execution of a presettable shift register 2 (sio2sfr) write instruction. if the slave sends data, the wait is immediately released by execution of an sio2sfr write instruction and the clock rises without the start transmission bit being output in the data line. therefore, as shown in figure 16-51, data should be transmitted by manipulating the p0a2 output latch through the program. at this time, control the low-level width ( a in figure 16-51 ) of the first serial clock at the timing used for setting the p0a2 output latch to 1 after execution of an sio2sfr write instruction. in addition, if the acknowledge signal from the master is not output (if data transmission from the slave is completed), set 1 in the sio2wrel flag and release the wait. for these timings, refer to figure 16-49 . figure 16-51. slave wait release (transmission) writing ffh to sio2sfr setting irqsio2 setting sio2ackd serial reception 9 a 23 a0 r ack d7 d6 d5 p0a2 output latch 1 setting irqsio2 ack output serial transmission write data to sio2sfr p0a2 output latch 0 wait release software operation hardware operation scl software operation hardware operation 1 sda master device operation transfer line slave device operation
276 pd17717, 17718, 17719 data sheet u12330ej2v0ds (3) slave wait release (slave reception) the slave is released from the wait status when the sio2wrel flag (bit 2 of the serial i/o2 interrupt timing specification register 1) is set or when an instruction that writes data to the presettable shift register 2 (sio2sfr) is executed. when the slave receives data, the first bit of the data sent from the master may not be received if the scl line immediately goes into a high-impedance state after an instruction that writes data to sio2sfr has been executed. this is because sio2sfr does not start operating if the scl line is in the high-impedance state while the instruction that writes data to sio2sfr is executed (until the next instruction is executed). therefore, receive the data by manipulating the output latch of p0a2 by program, as shown in figure 16-52. for this timing, refer to figure 16-48. figure 16-52. slave wait release (reception) writing data to sio2sfr setting irqsio2 setting sio2ackd serial transmission 923 a0 ack d7 d6 d5 p0a2 output latch 1 setting irqsio2 ack output serial reception write ffh to sio2sfr p0a2 output latch 0 wait release software operation hardware operation scl sda software operation hardware operation 1 w master device operation transfer line slave device operation
277 pd17717, 17718, 17719 data sheet u12330ej2v0ds (4) reception completion of salve in the reception completion processing of the slave, check the sio2cmdd flag of the serial i/o2sbi register 1 and sio2coi flag of the serial i/o2 operation mode register 0 (csim0) (when cmdd = 1). this is to avoid the situation where the slave cannot judge which of the start condition and data comes first and therefore, the wake-up condition cannot be used when the slave receives the undefined number of data from the master. 16.2.13 restrictions in i 2 c bus mode the following restrictions are applied to the pd17719. restrictions when used as slave device in i 2 c bus mode description: if the wake-up function is executed (by setting the bit 3 of the serial i/o2 operation mode register 1 to 1) in the serial transfer status note , the pd17719 checks the address of the data between the other slave and master. if that data happens to coincide with the slave address of the pd17719, the pd17719 takes part in communication, destroying the communication data. note the serial transfer status is the status since data has been written to the presettable shift register 2 (sio2sfr) until the interrupt request flag (irqsio2) is set to 1 by completion of the serial transfer. preventive measure: the above phenomenon can be avoided by modifying the program. before executing the wake-up function, execute the following program that clears the serial transfer status. when executing the wake-up function, do not execute an instruction that writes data to sio2sfr. even if such an instruction is not executed, data can be received while the wake-up function is executed. this program releases the serial transfer status. to release the serial transfer status, the serial interface 2 must be once disabled (by clearing the sio2csie flag (bit 3 of the serial i/o2 operation mode register 0 to 0). if the serial interface 2 is disabled in the i 2 c bus mode, however, the scl pin outputs a high level, and sda pin outputs a low level, affecting communication of the i 2 c bus. therefore, this program makes the scl and sda pins go into a high-impedance state to prevent the i 2 c bus from being affected. for the timing of each signal when this program is executed, refer to figure 16-48.
278 pd17717, 17718, 17719 data sheet u12330ej2v0ds example of program releasing serial transfer status set1 p0a3 : <1> clr1 p0abio3 : <2> clr1 p0abio2 : <3> clr1 sio2csie : <4> set1 sio2csie : <5> set1 sio2relt: <6> set1 p0abio2 : <7> clr1 p0a3 : <8> set1 p0abio3 : <9> <1> this instruction prevents the sda pin from outputting a low level when the i 2 c bus mode is restored by instruction <5>. the output of the sda pin goes into a high-impedance state. <2> this instruction sets the p0a3/sda pin in the input mode to protect the sda line from adverse influence when the port mode is set by instruction <4>. the p0a3/sda pin is set in the input mode when instruction <2> is executed. <3> this instruction sets the p0a2/scl pin in the input mode to protect the scl line from adverse influence when the port mode is set by instruction <4>. the p0a2/scl pin is set in the input mode when instruction <3> is executed. <4> this instruction changes the mode from i 2 c bus mode to port mode. <5> this instruction restores the i 2 c bus mode from the port mode. <6> this instruction prevents the sda pin from outputting a low level when instruction <8> is executed. <7> this instruction sets the p0a2 pin in the output mode because the p0a2 pin must be in the output mode in the i 2 c bus mode. <8> this instruction clears the output latch of the p0a3 pin to 0 because the output latch of the p0a3 pin must be set to 0 in the i 2 c bus mode. <9> this instruction sets the p0a3 pin in the output mode because the p0a3 pin must be in the output mode in the i 2 c bus mode. remark sio2relt: bit 0 of serial i/o2sbi register 1
279 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.2.14 scl/p0a2 and sck2/p0a1 pins output manipulation the scl/p0a2 and sck2/p0a1 pins can execute static output via software, in addition to outputting the normal serial clock. the number of serial clocks can also be arbitrarily set by software. the scl/p0a2 and sck2/p0a1 pins output should be manipulated as described below. (1) in 2-wire serial i/o mode the output level of the scl/p0a2 pin is manipulated by the p0a2 output latch. <1> set the serial i/o2 operation mode register 0 and 1 (scl pin is set in the output mode and serial operation is enabled). scl = 1 while serial transfer is stopped. <2> manipulate the content of the p0a2 output latch by executing the bit manipulation instruction. figure 16-53. scl/p0a2 pin configuration scl/p0a2 to internal logic p0a2 output latch sio2csie = 1 and sio2md0 = 1, respectively scl (1 while transfer is stopped) from serial clock controller manipulated by bit manipulation instruction
280 pd17717, 17718, 17719 data sheet u12330ej2v0ds (2) in i 2 c bus mode the output level of the scl/p0a2 pin is manipulated by the sio2clc flag of the serial i/o2 interrupt timing specification register 1. <1> set the sio2 operation mode registers 0 and 1 (scl pin is set in the output mode and serial operation is enabled). set 1 to the p0a2 output latch. scl = 0 while serial transfer is stopped. <2> manipulate the sio2clc flag by executing the bit manipulation instruction. figure 16-54. scl/p0a2 pin configuration note the level of the scl signal is in accordance with the contents of the logic circuits shown in figure 16- 55. figure 16-55. logic circuit of scl signal remarks 1. this figure indicates the relation of the signals and does not indicate the internal circuit. 2. sio2clc: bit 3 of serial i/o2 interrupt timing specification register 1 sio2clc (manipulated by bit manipulation instruction) wait request signal serial clock (low while transfer is stopped) scl scl/p0a2 to internal logic p0a2 output latch sio2csie = 1 and sio2md0 = 1, respectively scl note set 1 from serial clock controller
281 pd17717, 17718, 17719 data sheet u12330ej2v0ds (3) in 3-wire serial i/o mode the output level of the sck2/p0a1 pin is manipulated by the p0a1 output latch. <1> set the serial i/o2 operation mode registers 0 and 1 (sck2 pin is set in the output mode and serial operation is enabled). sck2 = 1 while serial transfer is stopped. <2> manipulate the content of the p0a1 output latch by executing the bit manipulation instruction. figure 16-56. sck2/p0a1 pin configuration 16.2.15 status of serial interface 2 at reset (1) at power-on reset each pin is set in the general-purpose input port mode. the contents of the presettable shift register 2 and serial i/o2 slave address register are undefined. (2) at wdt & sp reset each pin is set in the general-purpose input port mode. the contents of the presettable shift register 2 and serial i/o2 slave address register are undefined. (3) at ce reset each pin retains the previous status. the contents of the presettable shift register 2 and serial i/o2 slave address register are undefined. (4) on execution of clock stop instruction each pin is set in the general-purpose input port mode. the contents of the presettable shift register 2 and serial i/o2 slave address register are undefined. sck2/p0a1 to internal logic p0a1 output latch sio2csie = 1 and sio2md0 = 1, respectively sck2 (1 while transfer is stopped) from serial clock controller manipulated by bit manipulation instruction
282 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.3 serial interface 3 16.3.1 outline of serial interface 3 figure 16-57 shows the outline of serial interface 3. serial interface 3 can be used in uart and 3-wire serial i/o modes. figure 16-57. outline of serial interface 3 16.3.2 control registers of serial interface 3 serial interface 3 is controlled by the following four registers: serial i/o3 operation mode register serial i/o3 asynchronous status register serial i/o3 asynchronous mode register 0 serial i/o3 asynchronous mode register 1 sck3/p0b2 so3/txd/p0b1 si3/rxd/p0b0 clock i/o control block sio3csie flag sio3tcl0 and 1 flags clock control block 4.5 mhz clock counter wait control block sio3txe flag sio3ps0 and 1 flags sio3cl flag sio3sl flag transmission control block interrupt control block sio3txs sio3pe flag, sio3rxe flag sio3fe flag, sio3cl flag sio3ove flag, sio3ps0 and 1 flags sio3isrm flag reception control block baud rate generator receive shift register sio3rxb data i/o control block
283 pd17717, 17718, 17719 data sheet u12330ej2v0ds (1) serial i/o3 operation mode register figure 16-58 shows the configuration of the serial i/o3 operation mode register. this register controls the operation of 3-wire serial i/o mode, and select the clock to be used. figure 16-58. configuration of serial i/o3 operation mode register notes 1. this flag is ignored in any mode other than 3-wire serial i/o mode. 2. port 0b bit i/o select flag p0bbio1 must be set to 1 and the port latch must be set to 1. caution be sure to clear the sio3txe and sio3rxe flags of the serial i/o3 asynchronous mode register 0 to ??when using the 3-wire serial i/o mode. when using the uart mode, be sure to clear the sio3csie flag to ?? name flag symbol b 3 s i o 3 c s i e b 2 s i o 3 h i z b 1 s i o 3 t c l 1 b 0 s i o 3 t c l 0 address 1ah read/write r/w serial i/o3 operation mode register power-on reset wdt & sp reset ce reset clock stop 0 0 0 0 0 1 0 1 external clock 187.5 khz 375 khz 46.875 khz selects clock of 3-wire serial i/o general-purpose i/o port serial data output note 2 status of so3/p0b1 pin note 1 stops operation (wait status) enables operation of 3-wire serial i/o enables or stops operation of 3-wire serial i/o 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 at reset
284 pd17717, 17718, 17719 data sheet u12330ej2v0ds (2) serial i/o3 asynchronous status register figure 16-59 shows the configuration of the serial i/o3 asynchronous status register. this register indicates the nature of a reception error if any when the uart mode is used. the value of this register is cleared to 0 when data of the serial i/o3 receive buffer register (sio3rxe) is read. figure 16-59. configuration of serial i/o3 asynchronous status register name flag symbol b 3 b 2 s i o 3 p e b 1 s i o 3 f e b 0 s i o 3 o v e address 1bh read/write r serial i/o3 asynchronous status register power-on reset wdt & sp reset ce reset clock stop 0 0 1 when overrun does not occur or when data is read from serial i/o3 receive buffer register if data of serial i/o3 receive buffer register overlaps contents of serial i/o3 overrun error if framing error does not occur or if data is read from serial i/o3 receive buffer register if stop bit is not detected contents of serial i/o3 framing error if parity error does not occur, or if data is read from serial i/o3 receive buffer register if parity of transmit data does not coincide contents of serial i/o3 parity error 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 fixed to 0 at reset
285 pd17717, 17718, 17719 data sheet u12330ej2v0ds (3) serial i/o3 asynchronous mode register 0 this register sets the operation in the uart mode. figure 16-60 shows the configuration of the serial i/o3 asynchronous mode register 0. figure 16-60. configuration of serial i/o3 asynchronous mode register 0 caution be sure to clear the sio3csie flag of the serial i/o3 operation mode register to 0 when using the uart mode. clear the sio3txe and sio3rxe flags to 0 when using the 3- wire serial i/o mode. name flag symbol b 3 s i o 3 t x e b 2 s i o 3 r x e b 1 s i o 3 i s r m b 0 address 1dh read/write r/w serial i/o3 asynchronous mode register 0 power-on reset wdt & sp reset ce reset clock stop 0 0 0 0 fixed to 0 enables interrupt disables interrupt enables or disables generation of reception completion interrupt on occurrence of error stops operation uart mode (reception) uart mode (transmission) uart mode (transmission/reception) sets operation in uart mode 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 at reset
286 pd17717, 17718, 17719 data sheet u12330ej2v0ds (4) serial i/o3 asynchronous mode register 1 this register sets the parity bit, character length, and stop bit in the uart mode. figure 16-61 shows the configuration of the serial i/o3 asynchronous mode register 1. figure 16-61. configuration of serial i/o3 asynchronous mode register 1 caution be sure to rewrite this register when the operation in the uart mode is stopped. name flag symbol b 3 s i o 3 p s 1 b 2 s i o 3 p s 0 b 1 s i o 3 c l b 0 s i o 3 s l address 1ch read/write r/w serial i/o3 asynchronous mode register 1 power-on reset wdt & sp reset ce reset clock stop 0 0 0 0 0 1 number of stop bits = 1 number of stop bits = 2 specifies number of stop bits of uart transmit data 7 bits 8 bits specifies character length of uart no parity transmission: parity appended reception: parity error not generated odd parity even parity specifies parity bit of uart 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 at reset
287 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.3.3 serial i/o3 transmit register (sio3txs) and serial i/o3 receive buffer register (sio3rxb) both the serial i/o3 transmit register (sio3txs) and serial i/o3 receive buffer register (sio3rxb) are assigned to peripheral address 05h. sio3txs is a register that sets transmit data in the 3-wire serial i/o mode and uart mode. data b 6 through b 0 are transmitted when the character length is set to 7 bits in the uart mode. sio3rxb is a register that stores receive data in the 3-wire serial i/o mode and uart mode. data b 6 through b 0 are received, and b 7 is always 0 when the character length is set to 7 bits in the uart mode. when the put instruction is executed, the data of the data buffer is written to sio3txs. when the get instruction is executed, the data of sio3rxb is read to the data buffer. figure 16-62 shows the configuration of the serial i/o3 transmit register and serial i/o3 receive buffer register. figure 16-62. configuration of serial i/o3 transmit register and serial i/o3 receive buffer register caution do not write data to this register during operation in the 3-wire serial i/o mode. during transmission operation in the uart mode, this register is masked and no data can be written to it. peripheral register valid data dbf3 dbf2 dbf1 dbf0 data buffer transfer data don't care don't care 8 get (sio3rxb on execution of get) put (sio3txs on execution of put) name symbol peripheral address sio3txs sio3rxb 05h serial i/o3 transmit register, serial i/o3 receive buffer register b 7 m s b b 6 b 5 b 4 b 3 b 2 b 1 b 0 l s b setting of serial-out data and reading of serial-in data d7 d6 d5 d4 d3 d2 d1 d0 serial out (txs) serial in (rxb) d7 d6 d5 d4 d3 d2 d1 d0
288 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.3.4 operation of serial interface 3 serial interface 3 operates in the following two modes: 3-wire serial i/o mode uart mode table 16-10 shows the setting of each pin by each control flag in each operation mode. table 16-10. pin setting status by each control flag flag pin sss communication ss clock direction pin name s pppppp setting status of pin iii mode i i i 000000 ooo oo obbbbbb 333 33 3b2b1b0 ctr tt hiii sxx cc i o o o iee ll z210 e10 1 3-wire 0 0 external sck3/p0b2 0 external clock input serial i/o (slave) 1 general-purpose output port 0, 1 or internal 0 general-purpose input port 1, (master) 1 1 internal clock output so3/txd/p0b1 00 general-purpose input port 1 general-purpose output port 10 general-purpose input port 1 1 serial output si3/rxd/p0b0 0 serial input 1 general-purpose output port 0 1 0 uart so3/txd/p0b1 0 general-purpose input port (transmission) 1 1 serial output si3/rxd/p0b0 0 general-purpose input port 1 general-purpose output port 0 1 uart so3/txd/p0b1 0 general-purpose input port (reception) 1 general-purpose output port si3/rxd/p0b0 0 serial input 1 general-purpose output port 1 1 uart so3/txd/p0b1 0 general-purpose input port (transmission/ 1 1 serial output reception) si3/rxd/p0b0 0 serial input 1 general-purpose output port : don t care
289 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.3.5 3-wire serial i/o mode (1) outline of 3-wire serial i/o mode in the 3-wire serial i/o mode, communication is executed by using three pins: sck3, si3, and so3 pins. table 16-11 shows the outline of the 3-wire serial i/o mode. table 16-11. outline of 3-wire serial i/o mode pin used for communication sck3 pin (serial clock i/o pin) si3 pin (serial data input pin) so3 pin (serial data output pin) transmission/reception transmit data sequentially output from msb of shift register to data output pin in operation synchronization with falling of sck3 pin. receive data value of data input pin from lsb of shift register in synchronization with rising of sck3 pin. transmission/reception master transmission/reception is started by setting transfer data to transmit start register after 3-wire serial i/o master mode has been set. slave waits for clock from master with sck3 going into high-impedance state after 3-wire serial i/o slave mode has been set. interrupt issues interrupt request flag irqsio3 at rising of clock of 8th count clock pin master stops output of sck3 pin at rising of 8th count and retains high level until next transmission/reception is started slave goes into high-impedance state figure 16-63. serial bus configuration example in 3-wire serial i/o mode sck3 si3 so3 master slave sck3 so3 si3
290 pd17717, 17718, 17719 data sheet u12330ej2v0ds (2) timing chart figure 16-64 shows the timing chart in the 3-wire serial i/o mode. figure 16-64. timing chart in 3-wire serial i/o mode 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 transfer starts in synchronization with falling of sck3 end of transfer irqsio3 flag sck3 pin si3 pin so3 pin writing to shift register
291 pd17717, 17718, 17719 data sheet u12330ej2v0ds (3) program flowchart in 3-wire serial i/o mode an example of program flow chart in the 3-wire serial i/o mode is shown below. figure 16-65. example of flow chart in 3-wire serial i/o mode remark to execute a 3-wire serial i/o operation with the same setting as before, start from step <4>. <1> setting of pin (a) to input serial data from si3 pin set the i/o control mode of the si3 pin to 0 (input). (b) to output serial data from so3 pin set the i/o control mode of the so3 pin to 1 (output) and the port register of the so3 pin to 1 (output), respectively. in addition, set the sio3hiz flag of the serial /o3 operation mode register to 1 (at this point, the so3 pin outputs a high level). (c) setting of sck3 pin to output internal clock from sck3 pin set the port register of the so3 pin to 1 . in addition, select an internal clock by using the sio3tcl0 and 1 flags of the serial i/o3 operation mode register in step <2>. to input external clock to sck3 pin select an external clock by using the sio3tcl0 and 1 flags of the serial i/o3 operation mode register in step <2>. <1> setting of pin <2> setting of 3-wire serial i/o mode <3> setting of interrupt <4> writing to sio3txs and starting of transmission/reception end of transmission/reception (irqsio3 = 1) <5> interrupt routine yes no
292 pd17717, 17718, 17719 data sheet u12330ej2v0ds <2> setting 3-wire serial i/o transmission mode as communication mode set the following three by using the serial i/o3 operation mode register. 3-wire serial i/o mode clock so3 pin caution be sure to clear the sio3txe and sio3rxe flags to 0 . <3> setting of interrupt execute the ei instruction to set the ipsio3 flag to 1 . <4> setting of transmit data to sio3txs register start the 3-wire serial i/o transmission/reception operation as soon as the data has been set. output 8-bit transmit data from the so3 pin. store the serial data input from the si3 pin to the sio3rxb register as 8- bit receive data. <5> interrupt routine interrupt request flag irqsio3 is issued when the 3-wire serial i/o transmission/reception has been completed, and if the interrupt request is accepted, execution branches to a vector address.
293 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.3.6 uart mode the uart (universal asynchronous receiver/transmitter) mode is to transmit/receive 1-byte data following a start bit. in this mode, full-duplex operation can be executed. the baud rate is fixed to 9575 bps. (1) outline of uart mode table 16-12 shows the outline of the uart mode. table 16-12. outline of uart mode pins used for communication txd (serial data output pin. outputs high level when transmission is not executed) rxd (serial data input pin) transfer rate 9575 bps (automatic generation) first bit lsb transmission/reception transmit data data of 7 or 8 bits is transmitted from txd pin. operation start bit, parity bit, and stop bit are automatically generated. receive data data of 7 or 8 bits following start bit is received from rxd pin. reception errors such as parity error, framing error, and overrun error, are detected. starting transmission/ master transmission/reception is started by setting transfer data to transmit reception register after uart mode has been set. slave low level is input to rxd pin after uart mode has been set. if rxd pin remains low for about 52 s (9575 2 hz), it is recognized as start bit and reception is started. interrupt interrupt request irqsio3 is issued on completion of transmission, reception, or transmission/reception.
294 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.3.7 data format in uart mode (1) data format the format of the transmit/receive data is as shown in figure 16-66. one data frame consists of a start bit, character bits, a parity bit, and stop bit(s). the transfer rate is fixed to 9575 bps (automatically generated from the internal clock). figure 16-66. format of transmit/receive data in uart mode start bit .............. 1 bit character bits .... 7 or 8 bits parity bit ............. odd parity/even parity transmission: 0 parity reception: parity error does not occur. no parity stop bit ............... 1 or 2 bits (always 1 bit for reception) when the number of character bits is set to 7, only the low-order 7 bits (bits 0 through 6) are valid. when data is transmitted, the msb (bit 7) of the serial i/o transmit register (sio3txs) is ignored. when data is received, the msb (bit 7) of the serial i/o3 receive buffer register (sio3rxb) is always 0. if a reception error of serial data occurs, the nature of the error can be identified by reading the status of the serial i/o3 asynchronous status register. d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit 1 data frame
295 pd17717, 17718, 17719 data sheet u12330ej2v0ds (2) type and operation of parity the parity bit is used to detect a bit error in the communication data. usually, the same type of parity is used at the transmission and reception sides. odd parity and even parity can detect an error of 1 bit (the number of 1 s in data is odd). no error can be detected when 0 parity or no parity is used. table 16-13 shows the type and operation of parity. table 16-13. type and operation of parity even parity transmission if number of 1 s in transmit data is odd parity bit is 1 . if number of 1 s in transmit data is even parity bit is 0 . this controls number of 1 s included in transmit data and parity bit to be even. reception counts number of 1 s included in receive data and parity bit. if it is odd, parity error occurs. odd parity transmission if number of 1 s in transmit data is odd parity bit is 0 . if number of 1 s in transmit data is even parity bit is 1 . this controls number of 1 s included in transmit data and parity bit to be even. reception counts number of 1 s included in receive data and parity bit. if it is even, parity error occurs. 0 parity transmission clears parity bit to 0 regardless of transmit data. reception does not check parity bit. therefore, parity error does not occur regardless of whether parity bit is 0 or 1 . no parity transmission parity bit is not appended. reception reception is performed with no parity bit assumed. because no parity bit is used, parity error does not occur.
296 pd17717, 17718, 17719 data sheet u12330ej2v0ds (3) reception error three types of reception errors may occur: parity error, framing error, and overrun error. if the sio3isrm flag is 0 when a reception error occurs, the sio3 interrupt request (reception completion interrupt) is issued. if the sio3isrm flag is 1 , the sio3 interrupt request (reception completion interrupt) is not issued. the cause of the reception error can be detected by reading the serial i/o3 asynchronous status register after completion of the reception operation. the serial i/o3 asynchronous status register is cleared to 0 when the serial i/o3 receive buffer register (sio3rxb) is read. therefore, the serial i/o3 asynchronous status register must be read before the serial i/o3 receive buffer register is read. even if a reception error occurs, data is transferred to the serial i/o3 receive buffer register. table 16-14 describes each reception error. table 16-14. reception error parity error parity bit specified during transmission does not coincide with specified parity bit of receive data. framing error stop bit is not detected (rxd pin is low when stop bit is to be detected). overrun error reception of next data is completed before data is read from serial i/o3 receive buffer register. (4) detection of start bit the reception operation is enabled when the sio3rxe flag of the serial i/o3 asynchronous status register 0 is set to 1, and the rxd pin input is sampled. a start bit is recognized if the rxd pin is low about 52 s (9575 2 hz) after a low level has been input to the rxd pin, and the reception operation is started. if a low level is input to the rxd pin and the rxd pin goes high after about 52 s (9575 2 hz), the start bit is not recognized, and the reception operation is not started. at this time, the reception is enabled again, and the rxd pin input is sampled.
297 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.3.8 program flowchart in uart mode (1) flowchart in uart transmission mode here is an example of a program flowchart in the uart transmission mode. figure 16-67. flowchart example in uart transmission mode remark to execute transmission in the uart mode with the same setting as before, start from step <4>. <1> setting of pin (to output serial data from rxd pin) 1. set the p0bbio1 flag to 1 (output). 2. set the port register of the txd pin to 1 (at this point, the txd pin outputs a high level). <2> setting of interrupt execute the ei instruction and set the ipsio3 flag to 1 . <3> setting of uart 1. set the following in the serial i/o3 asynchronous mode register 1. parity bit character length stop bit 2. set the uart mode (transmission) by using the serial i/o3 asynchronous mode register 0. caution be sure to clear the sio3csie flag to 0 . <1> setting of pin <2> setting of interrupt <4> writing to sio3txs (starts transmission) end of transmission <5> interrupt routine yes no <3> setting of uart mode
298 pd17717, 17718, 17719 data sheet u12330ej2v0ds <4> set transmit data to the sio3txs register (start transmission) uart transmission is started as soon as data has been set. the txd pin outputs the start bit, transmit data (7 or 8 bits), parity bit, and stop bit (1 or 2 bits), and the transmission is completed. if the character length is 7 bits, however, the bit 7 (msb) of the sio3txs register is ignored. <5> interrupt routine when the uart transmission operation is completed, the interrupt request flag irqsio3 is issued. when this interrupt is accepted, execution branches to the vector address.
299 pd17717, 17718, 17719 data sheet u12330ej2v0ds (2) flowchart in uart reception mode here is an example of a program flowchart in the uart reception mode. figure 16-68. flowchart example in uart reception mode remark to execute reception in the uart mode with the same setting as before, start from step <4>. <1> setting of pin (to input serial data from rxd pin) set the p0bbio1 flag to 0 (input). <2> setting of interrupt execute the ei instruction and set the ipsio3 flag to 1 . <3> setting of uart 1. set the following in the serial i/o3 asynchronous mode register 1. parity bit character length the number of stop bits is 1 during reception, regardless of the setting. 2. set the following two to the serial i/o3 asynchronous mode register 0. uart mode (reception) reception completion interrupt in case of reception error caution be sure to clear the sio3csie flag to 0 . <1> setting of pin <2> setting of interrupt <4> detection of start bit (starts reception) end of reception <5> interrupt routine yes no <3> setting of uart mode
300 pd17717, 17718, 17719 data sheet u12330ej2v0ds <4> detection of start bit uart reception is started as soon as the start bit has been detected from the rxd pin. the rxd pin inputs the start bit, transmit data (7 or 8 bits), parity bit, and stop bit (1 bit) in that order. the received data is stored to the sio3rxb register and the reception is completed. <5> interrupt routine when the uart transmission operation is completed, the interrupt request flag irqsio3 is issued. when this interrupt is accepted, execution branches to the vector address. caution because the serial i/o3 asynchronous status register is cleared to 0 when the sio3rxb register has been read, read the serial i/o3 asynchronous status register and then the sio3rxb register.
301 pd17717, 17718, 17719 data sheet u12330ej2v0ds (3) flowchart in uart transmission/reception mode here is an example of a program flowchart in the uart transmission/reception mode. figure 16-69. flowchart example in uart transmission/reception mode remark to execute reception in the uart mode with the same setting as before, start from step <4>. caution this program flowchart shows an example where transmission and then reception have been completed in that order after transmission and reception have been started. in the following cases, the interrupt request irqsio3 flag of serial i/o3 may not be detected two times (completion of transmission/reception), unlike in the above flowchart: if transmission is completed before the irqsio3 flag is cleared to 0 after completion of transmission . if transmission is completed before the irqsio3 flag is cleared to 0 after completion of reception. <1> setting of pin <2> setting of interrupt <4> setting of transmit data to sio3txs register end of transmission yes no <3> setting of uart mode detection of start bit (starts transmission/reception) end of reception <6> interrupt routine (for reception) yes no <5> interrupt routine (for transmission) execution of ei instruction
302 pd17717, 17718, 17719 data sheet u12330ej2v0ds <1> setting of pin (to output serial data from txd pin and input serial data from rxd pin) 1. set the p0bbio1 flag to 1 (output). 2. set the port register of the txd pin to 1 (at this point, the txd pin outputs a high level). 3. set the p0bbio0 flag to 0 (input). <2> setting of interrupt execute the ei instruction and set the ipsio3 flag to 1 . <3> setting of uart 1. set the following in the serial i/o3 asynchronous mode register 1. parity bit character length stop bit the number of stop bits is 1 during reception, regardless of the setting. 2. set the following in the serial i/o3 asynchronous mode register 0. uart mode (transmittion/reception) reception completion interrupt in case of reception error caution be sure to clear the sio3csie flag to 0 . <4> set transmit data to the sio3txs register (start transmission) uart transmission is started as soon as data has been set. the txd pin outputs the start bit, transmit data (7 or 8 bits), parity bit, and stop bit (1 or 2 bits) in that order, and the transmission is completed. if the character length is 7 bits, however, the bit 7 (msb) of the sio3txs register is ignored. detection of start bit uart reception is started as soon as the start bit has been detected from the rxd pin. the rxd pin inputs the start bit, transmit data (7 or 8 bits), parity bit, and stop bit (1 bit) in that order. the received data is stored to the sio3rxb register and the reception is completed. <5> interrupt routine (for transmission) when the uart transmission operation is completed, the interrupt request flag irqsio3 is issued. when this interrupt is accepted, execution branches to the vector address. <6> interrupt routine (for reception) when the uart transmission operation is completed, the interrupt request flag irqsio3 is issued, and data is set to the serial i/o3 asynchronous status register (however, only if a reception error occurs). when this interrupt is accepted, execution branches to the vector address. caution because the serial i/o3 asynchronous status register is cleared to 0 when the sio3rxb register has been read, read the serial i/o3 asynchronous status register and then the sio3rxb register.
303 pd17717, 17718, 17719 data sheet u12330ej2v0ds 16.3.9 cautions on uart mode the data of sio3txs is other than ffh after the following uart operation. to execute uart transmission after that, be sure to set ffh to sio3txs and then set the sio3txe flag to 1. this is because the uart transmit shift clock operates and the data of sio3txs is output from the txd pin if the sio3txe flag is set to 1. if sio3txe is cleared to 0 during uart transmission. if sio3rxe is cleared to 0 during uart reception. after completion of transmission in the uart mode, and after completion of the operation in the 3-wire serial i/o mode, the data of sio3txs is ffh . 16.3.10 status of serial interface 3 at reset (1) at power-on reset each pin is set in the general-purpose input port mode. the contents of the serial i/o3 transmit register (sio3txs) and serial i/o3 receive buffer register (sio3rxb) are ffh. (2) at wdt & sp reset each pin is set in the general-purpose input port mode. the contents of the serial i/o3 transmit register and serial i/o3 receive buffer register are ffh. (3) at ce reset each pin is set in the general-purpose input port mode. the contents of the serial i/o3 transmit register and serial i/o3 receive buffer register are ffh. (4) on execution of clock stop instruction each pin is set in the general-purpose input port mode. the contents of the serial i/o3 transmit register and serial i/o3 receive buffer register are ffh.
304 pd17717, 17718, 17719 data sheet u12330ej2v0ds 17. pll frequency synthesizer the pll (phase locked loop) frequency synthesizer is used to lock a frequency in the mf (medium frequency), hf (high frequency), and vhf (very high frequency) to a constant frequency by means of phase difference comparison. 17.1 outline of pll frequency synthesizer figure 17-1 outlines the pll frequency synthesizer. a pll frequency synthesizer can be configured by connecting an external lowpass filter (lpf) and voltage controlled oscillator (vco). the pll frequency synthesizer divides a signal input from the vcoh or vcol pin by using a programmable divider and outputs a phase difference between this signal and a reference frequency from the eo0 and eo1 pins. the pll frequency synthesizer operates only while the ce pin is high. it is disabled when the ce pin is low. for the details of the disabled status of the pll frequency synthesizer, refer to 17.5 pll disabled status . figure 17-1. outline of pll frequency synthesizer input select block programmable divider (pd) reference frequency generator 4.5 mhz pllscnf flag dbf pllrfck3 flag pllrfck2 flag pllrfck1 flag pllrfck0 flag pllul flag pllmd1 flag pllmd0 flag vcoh vcol eo1 eo0 phase comparator ( -det) charge pump lowpass filter (lpf) voltage controlled oscillator (vco) unlock ff note note note external circuit remarks 1. pllmd1 and pllmd0 (bits 1 and 0 of pll mode selection register: refer to figure 17-3 ) selects a division mode of the pll frequency synthesizer. 2. pllscnf (bit 3 of pll mode selection register: refer to figure 17-3 ) selects the least significant bit of the swallow counter. 3. pllrfck3 through pllrfck0 (bits 3 through 0 of pll reference frequency selection register: refer to figure 17-6 ) selects a reference frequency fr of the pll frequency synthesizer. 4. pllul (bit 0 of pll unlock ff register: refer to figure 17-9 ) detects the pll unlock ff status.
305 pd17717, 17718, 17719 data sheet u12330ej2v0ds 17.2 input selection block and programmable divider 17.2.1 configuration and function of input selection block and programmable divider figure 17-2 shows the configuration of the input selection block and programmable divider. the input selection block selects an input pin and division mode of the pll frequency synthesizer. the vcoh or vcol pin can be selected as the input pin. the voltage on the selected pin is at the intermediate level (approx. 1/2 v dd ). the pin not selected is internally pulled down. because these pins are connected to an internal ac amplifier, cut the dc component of the input signal by connecting a capacitor in series to the pin. direct division mode and pulse swallow mode can be selected as division modes. the programmable divider divides the frequency of the input signal according to the value set to the swallow counter and programmable counter. the pin and division mode to be used are selected by the pll mode selection register. figure 17-3 shows the configuration of the pll mode selection register. the value of the programmable divider is set by using the pll data register via data buffer. figure 17-2. configuration of input selection block and programmable divider note pllscnf flag pllmd1 flag pllmd0 flag vcoh vcol pll disable signal 2- modulus prescaler 1/32, 1/33 programmable counter 12 bits f n -det swallow counter 5 bits 4 16 12 dbf pll data register 12 bits 4 bits r f note to
306 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 17-3. configuration of pll mode selection register 17.2.2 outline of each division mode (1) direct division mode (mf) in this mode, the vcol pin is used. the vcoh pin is pulled down. in this mode, only the programmable counter is used for frequency division. (2) pulse swallow mode (hf) in this mode, the vcol pin is used. the vcoh pin is pulled down. in this mode, the swallow counter and programmable counter are used for frequency division. name flag symbol b 3 p l l s c n f b 2 0 b 1 p l l m d 1 b 0 p l l m d 0 address 10h read/write r/w pll mode selection power-on reset wdt&sp reset ce reset 1 clock stop at reset 0 1 0 1 0 0 0 0 disables vcol and vcoh pins direct division (vcol pin, mf mode) pulse swallow (vcoh pin, vhf mode) pulse swallow (vcol pin, hf mode) selects division mode of pll frequency synthesizer u u r r u: undefined r: retained 0 0 0 1 1 fixed to 0 0 0 0 0 clears least significant bit to 0 sets least significant bit to 1 selects least significant bit of swallow counter 0 1
307 pd17717, 17718, 17719 data sheet u12330ej2v0ds (3) pulse swallow mode (vhf) in this mode, the vcoh pin is used. the vcol pin is pulled down. in this mode, the swallow counter and programmable counter are used for frequency division. (4) vcol and vcoh pin disabled in this mode, only the vcol and vcoh pins are internally pulled down, but the other blocks operate. 17.2.3 programmable divider and pll data register the programmable divider consists of a 5-bit swallow counter and a 12-bit programmable counter. each counter is a 17-bit binary down counter. the programmable counter is allocated to the high-order 12 bits of the pll data register, and the swallow counter is allocated to the low-order 4 bits. data are set to these counters via data buffer. the least significant bit of the swallow counter sets data to the pllscnf flag of the control register. the value by which the input signal frequency is to be divided is called ? value? for how to set a division value (n value) in each division mode, refer to 17.6 using pll frequency synthesizer . (1) pll data register and data buffer figure 17-4 shows the relationships between the pll data register and data buffer. in the direct division mode, the high-order 12 bits of the pll data register are valid, and all 17 bits of the register are valid in the pulse swallow mode. in the direct division mode, all 12 bits are used as a programmable counter. in the pulse swallow mode, the high-order 12 bits are used as a programmable counter, and the low-order 5 bits are used as a swallow counter. (2) relationship between division value n of programmable divider and divided output frequency the relationship between the value ? set to the pll data register and the signal frequency ? n divided and output by the programmable divider is as shown below. for details, refer to 17.6 using pll frequency synthesizer . (a) direct division mode (mf) f in = f in n: 12 bits n (b) pulse swallow mode (hf, vhf) f in = f in n: 17 bits n
308 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 17-4. setting division value (n value) of pll frequency synthesizer note the value of pllscnf flag is transferred when a write (put) instruction is executed to the pll data register (pllr). therefore, data must be set to the pllscnf flag before executing the write instruction to the pll data register. data buffer dbf3 dbf2 name pll data register symbol pllr peripheral address 42h dbf1 dbf0 b 3 b 2 b 1 b 0 b 3 b 0 b 0 b 1 b 1 b 2 b 2 b 3 b 3 b 4 b 4 b 5 b 5 b 6 b 6 b 7 b 7 b 8 b 8 b 9 b 9 b 10 b 10 b 11 b 11 b 12 b 12 b 13 b 13 b 14 b 14 b 15 b 15 b 16 b 6 b 5 b 4 b 10 b 9 b 8 b 7 b 13 b 12 b 15 b 14 b 11 peripheral register pll n value data (17 bits) direct division mode 0 don't care setting prohibited division value n: n = x setting prohibited division value n: n = x don't care don't care don't care 15 (00fh) 2 12 1 (fffh) pulse swallow mode transfer data valid data sets high-order 16 bits of division value sets least significant bit of division value note name pll mode selection address 10h b 3 p l l s c n f p l l m d 1 p l l m d 0 0 b 2 b 1 b 0 register file get put 16 sets division value (n value) of pll frequency synthesizer x 0 1023 (3ffh) 2 17 1 (1ffffh) x don't care 16 (010h) 1024 (400h)
309 pd17717, 17718, 17719 data sheet u12330ej2v0ds 17.3 reference frequency generator figure 17-5 shows the configuration of the reference frequency generator. the reference frequency generator generates the reference frequency fr of the pll frequency synthesizer by dividing the 4.5 mhz output of a crystal oscillator. thirteen frequencies can be selected as reference frequency fr: 1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 18, 20, 25, and 50 khz. the reference frequency fr is selected by the pll reference frequency selection register. figure 17-6 shows the configuration and function of the pll reference frequency selection registerion. figure 17-5. configuration of reference frequency generator pllrfck3 flag pllrfck2 flag pllrfck1 flag pllrfck0 flag mux 1 khz 1.25 khz 2.5 khz 25 khz 50 khz off pll disable signal to -det divider 4.5 mhz
310 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 17-6. configuration of pll reference frequency selection register remark when the pll frequency synthesizer is disabled by the pll reference frequency selection register, the vcoh and vcol pins are internally pulled down. the eo1 and eo0 pins are floated. name flag symbol b 3 p l l r f c k 3 b 2 p l l r f c k 2 b 1 p l l r f c k 1 b 0 p l l r f c k 0 address 11h read/write r/w pll reference frequency selection power-on reset wdt&sp reset ce reset clock stop at reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1.25 khz 2.5 khz 5 khz 10 khz 6.25 khz 12.5 khz 25 khz 50 khz 3 khz 9 khz 18 khz setting prohibited 1 khz 20 khz setting prohibited pll disable sets reference frequency f r of pll frequency synthesizer 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1
311 pd17717, 17718, 17719 data sheet u12330ej2v0ds 17.4 phase comparator ( -det), charge pump, and unlock ff 17.4.1 configuration of phase comparator, charge pump, and unlock ff figure 17-7 shows the configuration of the phase comparator, charge pump, and unlock ff. the phase comparator compares the phase of the divided frequency f n output by the programmable divider with the phase of the reference frequency fr output by the reference frequency generator, and outputs an up (up) or down (dw) request signal. the charge pump outputs the output of the phase comparator from an error out pin (eo1 and eo0 pins). the unlock ff detects the unlock status of the pll frequency synthesizer. 17.4.2 through 17.4.4 describe the operations of the phase comparator, charge pump, and unlock ff. figure 17-7. configuration of phase comparator, charge pump, and unlock ff unlock ff pllul flag up f r f n charge pump eo1 eo0 reference frequency generator programmable divider dw pll disable si g nal phase comparator ( - det)
312 pd17717, 17718, 17719 data sheet u12330ej2v0ds 17.4.2 function of phase comparator as shown in figure 17-7, the phase comparator compares the phases of the divided frequency f n output by the programmable divider and the reference frequency fr , and outputs an up or down request signal. if the divided frequency f n is lower than reference frequency fr, the up request signal is output. if f n is higher than fr, the down request signal is output. figure 17-8 shows the relationship between reference frequency fr, divided frequency f n , up request signal, and down request signal. when the pll frequency synthesizer is disabled, neither the up request nor the down request signal is output. the up and down request signals are input to the charge pump and unlock ff, respectively. figure 17-8. relationship between fr, f n , up, and dw (a) if f n lags behind fr (b) if f n leads fr (c) if f n and fr are in phase (d) if f n is lower than fr f r f n up dw f r f n up dw f r f n up dw f r f n up dw
313 pd17717, 17718, 17719 data sheet u12330ej2v0ds 17.4.3 charge pump as shown in figure 17-7, the charge pump outputs the up request and down request signals output by the phase comparator, from the error out pins (eo1 and eo0 pins). therefore, the relationship between the output of the error out pins, divided frequency f n and reference frequency fr is as follows: where reference frequency fr > divided frequency f n : low-level output where reference frequency fr < divided frequency f n : high-level output where reference frequency fr = divided frequency f n : floating 17.4.4 unlock ff as shown in figure 17-7, the unlock ff detects the unlock status of the pll frequency synthesizer from the up request and down request signals of the phase comparator. because either the up request or down request signal is low in the unlock status, the unlock status is detected by this low-level signal. in the unlock status, the unlock ff is set to 1. the unlock ff is set in the cycle of the reference frequency fr selected at that time. when the contents of the pll unlock ff register are read (by the peek instruction), the unlock ff is reset (read & reset). therefore, the unlock ff must be detected in a cycle longer than cycle 1/fr of the reference frequency fr. the status of the unlock ff is detected by the pll unlock ff register. figure 17-9 shows the configuration of the pll unlock ff register. because this register is a read-only register, its contents can be read to the window register by the peek instruction. because the unlock ff is set in a cycle of the reference frequency fr, the contents of the pll unlock ff register are read to the window register in a cycle longer than cycle 1/fr of the reference frequency. the delay time of the up and down request signals of the phase comparator are fixed to 0.8 to 1.0 s.
314 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 17-9. configuration of pll unlock ff register name flag symbol b 3 0 b 2 0 b 1 0 b 0 p l l u l address 12h read/write r & reset pll unlock ff power-on reset wdt&sp reset ce reset u: undefined r: retained clock stop at reset 0 1 u u r r unlock ff = 0: pll locked status unlock ff = 1: pll unlocked status fixed to 0 detects status of unlock ff 000
315 pd17717, 17718, 17719 data sheet u12330ej2v0ds 17.5 pll disabled status the pll frequency synthesizer stops (is disabled) while the ce pin is low. likewise, it also stops when pll disabled status is selected by the pll reference frequency register (rf address 11h). table 17-1 shows the operation of each block in the pll disabled status. when the vcol and vcoh pins are disabled by the pll mode selection register, only the vcol and vcoh pins are internally pulled down, and the other blocks operate. because the pll frequency selection register and pll mode selection register are not initialized at ce reset (hold the previous status), these registers return to the previous status when the ce pin has gone low, the pll frequency synthesizer has been disabled, and then ce pin has gone high. to disable the pll frequency synthesizer at ce reset, initialize these registers in software. at power-on reset, the pll frequency synthesizer is disabled. table 17-1. operation of each block under each pll disable condition condition ce pin = low level ce pin = high level (pll disabled) pll reference frequency pll mode selection selection register = 1111b register = 0000b each block (pll disabled) (vcoh and vcol disabled) vcol, vcoh pins internally pulled down internally pulled down internally pulled down programmable divider division stopped division stopped operates reference frequency generator output stopped output stopped operates phase comparator output stopped output stopped operates charge pump error out pins are floated error out pins are floated operates. however, usually outputs low level because no signal is input
316 pd17717, 17718, 17719 data sheet u12330ej2v0ds 17.6 using pll frequency synthesizer to control the pll frequency synthesizer, the following data is necessary. (1) division mode : direct division (mf), pulse swallow (hf, vhf) (2) pins used : vcol and vcoh pins (3) reference frequency : fr (4) division value : n 17.6.1 through 17.6.3 below describe how to set pll data in each division mode (mf, hf, and vhf). 17.6.1 direct division mode (mf) (1) selecting division mode select the direct division mode by using the pll mode selection register. (2) pins used the vcol pin is enabled to operate when the direct division mode is selected. (3) selecting reference frequency fr select the reference frequency by using the pll reference frequency selection register. (4) calculation of division value n calculate n as follows: n = f vcol fr f vcol : input frequency of vcol pin fr : reference frequency (5) example of setting pll data how to set data to receive broadcasting in the following mw band is described below. reception frequency : 1422 khz (mw band) reference frequency : 9 khz intermediate frequency : +450 khz division value n is calculated as follows: n = f vcol = 1422 + 450 = 208 (decimal) fr 9 = 0d0h (hexadecimal) set data to the pll data register, pll mode selection register, and pll reference frequency selection register as follows:
317 pd17717, 17718, 17719 data sheet u12330ej2v0ds notes 1. pllscnf flag 2. don t care pll data register (pllr) 0 0 0 0 0 0 0 0 0 0 don't care 1 1 0 1 d pll mode selection register pll reference frequency selection register note 1 note 2 1 1 0 1 9 khz 0 0 1 mf
318 pd17717, 17718, 17719 data sheet u12330ej2v0ds 17.6.2 pulse swallow mode (hf) (1) selecting division mode select the pulse swallow mode by using the pll mode selection register. (2) pins used the vcol pin is enabled to operate when the pulse swallow mode is selected. (3) selecting reference frequency fr select the reference frequency by using the pll reference frequency selection register. (4) calculation of division value n calculate n as follows: n = f vcol fr f vcol : input frequency of vcol pin fr : reference frequency (5) example of setting pll data how to set data to receive broadcasting in the following sw band is described below. reception frequency : 25.50 mhz (sw band) reference frequency : 5 khz intermediate frequency: +450 khz division value n is calculated as follows: n = f vcol = 25500 + 450 = 5190 (decimal) fr 5 = 1446h (hexadecimal) set data to the pll data register, pll mode selection register, and pll reference frequency selection register as follows: caution the division value n is 17 bits long when the pulse swallow mode is selected, and the least significant bit of the swallow counter is the bit 3 of the pll mode selection register (pllscnf). to set ?446h as the division value n, the value to be actually set to the pll data register is ?a23h? note pllscnf flag pll data register (pllr) 0 0 0 0 0 0 1 00 0 1 1 1 0 1 0 pll mode selection register pll reference frequency selection register note 0 0 0 1 0 0 1 1 5 khz hf 6 4 4 1
319 pd17717, 17718, 17719 data sheet u12330ej2v0ds 17.6.3 pulse swallow mode (vhf) (1) selecting division mode select the pulse swallow mode by using the pll mode selection register. (2) pins used the vcoh pin is enabled to operate when the pulse swallow mode is selected. (3) selecting reference frequency fr select the reference frequency by using the pll reference frequency selection register. (4) calculation of division value n calculate n as follows: n = f vcoh fr f vcoh : input frequency of vcoh pin fr : reference frequency (5) example of setting pll data how to set data to receive broadcasting in the following fm band is described below. reception frequency : 98.15 mhz (fm band) reference frequency : 50 khz intermediate frequency : +10.7 mhz division value n is calculated as follows: n = f vcoh = 98.15 + 10.7 = 2177 (decimal) fr 0.050 = 0881h (hexadecimal) set data to the pll data register, pll mode selection register, and pll reference frequency selection register as follows: caution the division value n is 17 bits long when the pulse swallow mode is selected, and the least significant bit of the swallow counter is the bit 3 of the pll mode selection register (pllscnf). to set 0881h as the division value n, the value to be actually set to the pll data register is 0440h . pll data register (pllr) 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 pll mode selection register pll reference frequency selection register note 1 0 1 0 50 khz vhf 1 8 8 0 0 1 1 1 note pllscnf flag
320 pd17717, 17718, 17719 data sheet u12330ej2v0ds note that data must be set to the pllscnf flag before a write (put) instruction is executed to the pll data register (pllr). example set1 pllscnf mov dbf0, #0 mov dbf1, #4 mov dbf2, #4 put pllr, dbf 17.7 status at reset 17.7.1 at power-on reset the pll frequency synthesizer is disabled because the pll reference frequency selection register is initialized to 1111b. 17.7.2 at wdt&sp reset the pll frequency synthesizer is disabled because the pll reference frequency selection register is initialized to 1111b. 17.7.3 on execution of clock stop instruction the pll frequency synthesizer is disabled because the pll reference frequency selection register is initialized to 1111b. 17.7.4 at ce reset the pll frequency synthesizer is disabled because the pll reference frequency selection register is initialized to 1111b. 17.7.5 in halt status the set status is retained if the ce pin is high.
321 pd17717, 17718, 17719 data sheet u12330ej2v0ds 18. frequency counter 18.1 outline of frequency counter figure 18-1 outlines the frequency counter. the frequency counter has an if counter function to count the intermediate frequency (if) of an external input signal and an external gate counter (fcg: frequency counter for external gate signal) to detect the pulse width of an external input signal. the if counter function counts the frequency input to the p1c0/fmifc or p1c1/amifc pin at fixed intervals (1 ms, 4 ms, 8 ms, or open) by using a 16-bit counter. the external gate counter function counts the frequency of the internal clock (1 khz, 100 khz, 900 khz) from the rising to the falling of the signal input to the p2a1/fcg1 or p2a0/fcg0 pin. the if counter and external gate counter functions cannot be used at the same time. figure 18-1. outline of frequency counter i/o selection block gate time control block start/stop control block if counter (16 bits) p2a1/fcg1 fcgch1 flag fcgch0 flag ifcck1 flag ifcck0 falg ifcstrt flag dbf ifcgostt flag ifcres flag ifcmd1 flag ifcmd0 fla g p2a0/fcg0 p1c0/fmifc p1c1/amifc remarks 1. fcgch1 and fcgch0 (bits 1 and 0 of fcg channel selection register: refer to figure 18-4 ) select the pin used for the external gate counter function. 2. ifcmd1 and ifcmd0 (bits 3 and 2 of if counter mode selection register: refer to figure 18-3 ) select the if counter or external gate counter function. 3. ifcck1 and ifcck0 (bits 1 and 0 of if counter mode selection register: refer to figure 18-3 ) select the gate time of the if counter function and the reference frequency of the external gate counter function. 4. ifcstrt (bit 1 of if counter control register: refer to figure 18-6 ) control starting of the if counter and external gate counter functions. 5. ifcgostt (bit 0 of if counter gate status detection register: refer to figure 18-7 ) detects opening/ closing the gate of the if counter function. 6. ifcres (bit 0 of if counter control register: refer to figure 18-6 ) reset the count value of the if counter.
322 pd17717, 17718, 17719 data sheet u12330ej2v0ds 18.2 input/output selection block and gate time control block figure 18-2 shows the configuration of the input/output selection block and gate time control block. the input/output selection block consists of an if counter input selection block and fcg i/o selection block. the if counter input selection block selects whether the frequency counter is used as an if counter or an external gate counter, by using the if counter mode register. when the frequency counter is used as the if counter, either p1c0/fmifc or p1c1/amifc pin and a count mode are selected. the pin not used for the if counter is used as a general-purpose input port pin. the fcg i/o selection block selects the p2a1/fcg1 or p2a0/fcg0 pin by using the fcg channel selection register, when the frequency counter is used as the external gate counter. the pin not used is used as a general- purpose i/o port pin. when using the frequency counter as the external gate counter, the pin to be used must be set in the input mode by using the port 2a bit i/o selection register. this is because the pin is set in the general-purpose output port mode if it is set in the output mode even if the external gate counter function is selected by the if counter mode selection register and fcg channel selection register. the gate time control block selects gate time by using the if counter mode selection register when the frequency counter is used as the if counter, or a count frequency when the frequency counter is used as the external gate counter. figure 18-3 shows the configuration of the if counter mode selection register. figure 18-4 shows the configuration of the fcg channel selection register. figure 18-2. configuration of i/o selection block and gate time control block 1/2 p2a1/fcg1 p2a0/fcg0 p1c0/fmifc p1c1/amifc input port fmifc amifc gate signal generator frequency generator selector frequency gate signal to start/stop control block i/o port fcgch1 flag fcgch0 flag ifcmd1 flag ifcmd0 flag fcg ifcck1 flag ifcck0 flag selector
323 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 18-3. configuration of if counter mode selection register caution the if counter and external gate counter functions cannot be used at the same time. name flag symbol b 3 i f c m d 1 b 2 i f c m d 0 b 1 i f c c k 1 b 0 i f c c k 0 address 22h read/write r/w if counter mode selection power-on reset wdt&sp reset ce reset clock stop at reset 0 1 0 1 0 0 0 0 1 ms 4 ms 8 ms open 1 khz 100 khz 900 khz setting prohibited selects gate time of if counter and reference frequency of external gate counter gate time of if counter reference frequency of external gate counter 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 external gate counter (fcg) if counter (amifc pin, amif count mode) if counter (fmifc pin, fmif count mode, 1/2 division) if counter (fmifc pin, amif count mode) selects function of if counter or external gate counter 0 0 1 1
324 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 18-4. configuration of fcg channel selection register name flag symbol b 3 0 b 2 0 b 1 f c g c h 1 b 0 f c g c h 0 address 20h read/write r/w fcg channel selection power-on reset wdt&sp reset ce reset clock stop at reset 0 1 0 1 0 0 0 0 fcg not used (general-purpose i/o port) p2a0/fcg0 pin p2a1/fcg1 pin setting prohibited fixed to 0 selects pin used for fcg 00 0 0 1 1 0 0 0 0
325 pd17717, 17718, 17719 data sheet u12330ej2v0ds 18.3 start/stop control block and if counter 18.3.1 configuration of start/stop control block and if counter figure 18-5 shows the configuration of the start/stop control block and if counter. the start/stop control block starts the frequency counter or detects the end of counting. the counter is started by the if counter control register. the end of counting is detected by the if counter gate status detection register. when the external gate counter function is used, however, the end of counting cannot be detected by the if counter gate status detection register. figure 18-6 shows the configuration of the if counter control register. figure 18-7 shows the configuration of the if counter gate status detection register. 18.3.2 and 18.3.3 describe the gate operation when the if counter function is selected and that when the external gate counter function is selected. the if counter is a 16-bit binary counter that counts up the input frequency when the if counter function or external gate counter function is selected. when the if counter function is selected, the frequency input to a selected pin is counted while the gate is opened by an internal gate signal. the frequency count is counted without alteration in the amif count mode. in the fmif counter mode, however, the frequency input to the pin is halved and counted. when the external gate counter function is selected, the internal frequency is counted while the gate is opened by the signal input to the pin. when the if counter counts up to ffffh, it remains at ffffh until reset. the count value is read by the if counter data register (ifc) via data buffer. the count value is reset by the if counter control register. figure 18-8 shows the configuration of the if counter data register. figure 18-5. configuration of start/stop control block and if counter start/stop control if counter (16 bits) 16 if counter data register (ifc) dbf ifcstrt flag ifcres flag ifcgostt flag gate signal frequency from gate time selection block 16 res
326 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 18-6. configuration of if counter control register name flag symbol b 3 0 b 2 0 b 1 i f c s t r t b 0 i f c r e s address 23h read/write w if counter control 0 1 nothing is affected resets counter resets data of if counter and external gate counter nothing is affected resets counter fixed to 0 start if counter and external gate counter 0 1 power-on reset wdt&sp reset ce reset clock stop at reset 0 0 0 0 0 00 0 0 0
327 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 18-7. configuration of if counter gate status detection register cautions 1. do not read the contents of the if counter data register (ifc) to the data buffer while the ifcgostt flag is set to 1. 2. the gate of the external gate counter cannot be opened or closed by the ifcgostt flag. use the ifcstrt flag to open or close the gate. name flag symbol b 3 0 b 2 0 b 1 0 b 0 i f c g o s t t address 21h read/write r if counter gate status detection 0 1 detects opening/closing of gate of frequency counter when if counter function is selected when external gate counter function is selected fixed to 0 power-on reset wdt&sp reset ce reset clock stop at reset 0 0 0 0 0 00 sets ifcstrt flag to 1 and is set to 1 until gate is closed sets ifcstrt flag to 1 and is set to 1 while gate is open, regardless of input of p2a0/fcg0 and p2a1/fcg1 pins
328 pd17717, 17718, 17719 data sheet u12330ej2v0ds 18.3.2 operation of gate when if counter function is selected (1) when gate time of 1, 4, or 8 ms is selected the gate is opened for 1, 4, or 8 ms from the rising of the internal 1-khz signal after the ifcstrt flag has been set to 1, as illustrated below. while this gate is open, the frequency input from a selected pin is counted by a 16-bit counter. when the gate is closed, the ifcg flag is cleared to 0. the ifcgostt flag is automatically set to 1 when the ifcstrt flag is set. (2) when gate is open if opening of the gate is selected by the ifcck1 and ifcck0 flags, the gate is opened as soon as its opening has been selected, as illustrated below. if the counter is started by using the ifcstrt flag while the gate is open, the gate is closed after undefined time. to open the gate, therefore, do not set the ifcstrt flag to 1. however, the counter can be reset by the ifcres flag. sets ifcck1 = ifcck0 = 1 gate is actually opened at this point. if g ate is opened while ifcgostt fla g is 1, it is closed after undefined time count period gate is closed after undefined time if ifcstrt flag is set during this period h internal 1 khz l open close gate the gate is opened or closed in the following two ways when opening the gate is selected as the gate time. gate is actually opened at this point count period (ifcgostt flag = 1) ifcstrt flag is set ifcgostt flag is set at this point end of counting ifgostt flag is cleared h internal 1 khz 1 ms gate time 4 ms 8 ms l open close
329 pd17717, 17718, 17719 data sheet u12330ej2v0ds (a) resetting the gate to other than open by using ifcck1 and ifcck0 flags (b) unselect pin used by using ifcmd1 and ifcmd0 flags in this way, the gate remains open, and counting is stopped by disabling input from the pin. 18.3.3 gate operation when external gate counter function is selected the gate is opened from the rising to the next rising of the signal input to a selected pin after the ifcstrt flag has been set to 1, as illustrated below. while the gate is open, the internal frequency (1 khz, 100 khz, 900 khz) is counted by a 16-bit counter. the ifcgostt flag is set to 1 from the rising to the next rising of the external signal after the ifcstrt flag has been set. in other words, the opening or closing of the gate cannot be detected by the ifcg flag when the external gate counter function is selected. if reset and started while gate is open ifcck1 = ifcck0 = 1 count period resetting the gate to other than open by ifcck1 and ifcck0 flags open gate close gate open close sets ifcck1 = ifcck0 = 1 count period sets ifcmd1 = ifcmd0 = 0 (fcg) fmifc and amifc pins are unselected and count signal cannot be input h l open close external signal gate count period gate is opened at this point end of counting ifcgostt flag is 0 ifcstrt flag 1 h l open close external signal gate count period count period ifcstrt flag 1 gate is opened at this point end of counting ifcgostt flag is 0 ifcstrt flag 1
330 pd17717, 17718, 17719 data sheet u12330ej2v0ds 18.3.4 function and operation of 16-bit counter the 16-bit counter counts up the frequency input within selected gate time. the 16-bit counter can be reset by writing 1 to the ifcres flag of the if counter control register. once the 16-bit counter has counted up to ffffh, it remains at ffffh until it is reset. the following paragraphs (1) and (2) describe the operations when the if counter function is selected and when the external gate counter function is selected. the value of the if counter data register is read via data buffer. figure 18-8 shows the configuration and function of the if counter data register. (1) when if counter is selected the frequency input to the p1c0/fmifc or p1c1/amifc pin is counted while the gate is open. note, however, that the frequency input to the p1c0/fmifc is divided by two and counted. the relationship between count value x (decimal) and input frequencies (f fmifc and f amifc ) is shown below. fmifc f fmifc = x 2 (khz) t gate : gate time (1 ms, 4 ms, 8 ms) t gate amifc f amifc = x (khz) t gate : gate time (1 ms, 4 ms, 8 ms) t gate (2) when external gate counter (fcg) is selected the internal frequency is counted while the gate is opened by the signal input to the p2a1/fcg1 or p2a0/ fcg0 pin. the relationship between the count value x (decimal) and the gate width t gate of the input signal is shown below. t gate = x (ms) fr: internal frequency (1, 100, 900 khz) fr
331 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 18-8. configuration of if counter data register data buffer dbf3 dbf2 name if counter data register symbol ifc peripheral address 43h dbf1 dbf0 b 3 b 2 b 1 b 0 b 6 b 5 b 4 b 10 b 9 b 8 b 7 b 13 b 12 b 15 b 14 b 11 peripheral register 0 transfer data valid data get can be executed put changes nothing 16 count value of frequency counter x 2 16 1 (ffffh) if counter function fmif count mode of fmifc pin counts rising edge of signal input to p1c0/fmifc pin via 1/2 divider amif count mode of amifc pin counts rising edge of signal input to p1c1/amifc pin amif count mode of fmifc pin counts rising edge of signal input to p1c0/fmifc pin external gate counter function counts rising edge of internal reference frequency signal from rising edge to next rising edge of signal input to p2a0/fcg0 or p2a1/fcg1 pin once the if counter data register has counted up to ffffh, it remains at ffffh until the counter is reset.
332 pd17717, 17718, 17719 data sheet u12330ej2v0ds 18.4 using if counter the following sections 18.4.1 through 18.4.3 describe how to use the hardware of the if counter, a program example, and count error. 18.4.1 using hardware of if counter figure 18-9 shows the block diagram when the p1c0/fmifc and p1c1/amifc pins. as shown in the figure, the if counter uses an input pin with an ac amplifier, the dc component of the input signal must be cut with a capacitor. when the p1c0/fmifc or p1c1/amifc pin is selected for the if counter function, switch sw turns on, and the voltage level on each pin reaches about 1/2v dd . if the voltage has not risen to a sufficient intermediate level at this time, the if counter does not operate normally because the ac amplifier is not in the normal operating range. therefore, make sure that a sufficient wait time elapses after each pin has been specified to be used for the if counter until counting is started. figure 18-9. if count function block diagram of each pin to internal counter sw r c fmifc amifc external frequecny
333 pd17717, 17718, 17719 data sheet u12330ej2v0ds 18.4.2 program example of if counter a program example of the if counter is shown below. as shown in this example, make sure that a wait time elapses after an instruction that selects the p1c0/fmifc or p1c1/amifc pin for the if counter function has been executed until counting is started. this is because, as described in 18.4.1, the internal ac amplifier does not operate normally immediately after a pin has been selected for the if counter. example to count the frequency input to the p1c0/fmifc pin (fmif count mode) (gate time: 8 ms) initflg ifcmd1, not ifcmd0, ifcck1, not ifcck0 ; selects fmifc pin (fmif count mode), and sets gate time to 8 ms wait ; internal ac amplifier stabilization time set1 ifcres ; resets counter set1 ifcstrt ; starts counting loop: skt1 ifcg0stt ; detects opening or closing of gate br read ; branches to read: if gate is closed processing a br loop ; do not read data of if counter with this processing a read: get dbf, ifc ; reads value of if counter data register to data buffer 18.4.3 error of if counter the errors of the if counter include a gate time error and a count error. the following paragraphs (1) and (2) describe each of these errors. (1) gate time error the gate time of the if counter is created by dividing the 4.5-mhz clock. therefore, if the system clock is shifted from 4.5 mhz by +x ppm, the gate time is shifted by x ppm. (2) count error the if counter counts frequency by the rising edge of the input signal. if a high level is input to the pin when the gate is open, therefore, one excess pulse is counted. if the gate is closed, however, a count error due to the status of the pin does not occur. therefore, the count error is +1, 0 .
334 pd17717, 17718, 17719 data sheet u12330ej2v0ds 18.5 using external gate counter 18.5.1 program example of external gate counter a program example of the external gate counter is shown below. example to use the p2a0/fcg0 pin as external gate input pin initflg not ifcmd1, not ifcmd0, ifcck1, not ifcck0 ; selects external gate counter function and sets gate time to 8 ms initflg not fcgch1, fcgch0 ; selects fcg0 pin as external gate input pin set1 ifcres ; resets counter set1 ifcstrt ; starts counting loop: skf1 ifcgostt ; detects opening or closing of gate br read ; branches to read: if gate is closed processing a ; do not read data of if counter with this processing a br loop read: get dbf, ifc ; reads value of if counter data register to data buffer 18.5.2 error of external gate counter the errors of the external gate counter include an internal frequency error and a count error. the following paragraphs (1) and (2) describe each of these errors. (1) internal frequency error the internal frequency of the external gate counter is created by dividing the 4.5-mhz clock. therefore, if the system clock is shifted from 4.5 mhz by +x ppm, the gate time is shifted by x ppm. (2) count error the external gate counter counts the frequency by the rising edge of the internal frequency. if the internal frequency is low when the gate is opened (when the signal input to the pin rises), one excess pulse is counted. if the gate is closed (when the signal rises next time), the excess pulse is not counted due to the count level of the internal frequency. therefore, the count error is +1, 0 .
335 pd17717, 17718, 17719 data sheet u12330ej2v0ds 18.6 status at reset 18.6.1 at power-on reset the p1c0/fmifc, p1c1/amifc, p2a0/fcg0, and p2a1/fcg1 pins are set in the general-purpose input port mode. 18.6.2 at wdt&sp reset the p1c0/fmifc, p1c1/amifc, p2a0/fcg0, and p2a1/fcg1 pins are set in the general-purpose input port mode. 18.6.3 on execution of clock stop instruction the p1c0/fmifc and p1c1/amifc pins are set in the general-purpose input port mode. the p2a0/fcg0 and p2a1/fcg1 pins are set in the general-purpose i/o port mode, and retain the previous input or output status. 18.6.4 at ce reset the p1c0/fmifc and p1c1/amifc pins are set in the general-purpose input port mode. the p2a0/fcg0 and p2a1/fcg1 pins are set in the general-purpose i/o port mode, and retain the previous input or output status. 18.6.5 in halt status the p1c0/fmifc, p1c1/amifc, p2a0/fcg0, and p2a1/fcg1 pins retain the status immediately before the halt mode is set.
336 pd17717, 17718, 17719 data sheet u12330ej2v0ds 19. beep 19.1 outline of beep figure 19-1 outlines beep. beep outputs a clock of 1, 3, 4, or 6.7 khz from the p1d0/beep0 pin, and a clock of 4 khz, 3 khz, 200 hz, or 67 hz from the p1d1/beep1 pin. the duty factor of the beep output is 50%. figure 19-1. outline of beep p1d0/beep0 p1d1/beep1 p1dbio0 flag beep0sel flag beep0ck1 falg beep0ck0 falg p1dbio1 flag beep1sel flag beep1ck1 flag beep1ck0 flag i/o selection block output selection flag clock selection block i/o selection block output selection flag clock selection block output latch output latch clock generation block 1 khz 3 khz 4 khz 6.7 khz 67 hz 200 hz remarks 1. beep0ck1 and beep0ck0 (bits 1 and 0 of beep clock selection register: refer to figure 19-4 ) select the output frequency of beep0. 2. beep1ck1 and beep1ck0 (bits 3 and 2 of beep clock selection register: refer to figure 19-4 ) select the output frequency of beep1. 3. beep1sel and beep0sel (bits 1 and 0 of beep/general-purpose port pin function selection register: refer to figure 19-3 ) select general-purpose i/o port and beep. 4. p1dbio1 and p1dbio0 (bits 1 and 0 of port 1d bit i/o selection register: refer to figure 19-2 ) select the input or output mode of the port.
337 pd17717, 17718, 17719 data sheet u12330ej2v0ds 19.2 i/o selection block and output selection block the i/o selection block selects the input or output mode of the p1d0/beep0 and p1d1/beep1 pins by using the port 1d bit i/o selection register. set the pin to be used as a beep pin in the output mode. the output selection block sets the p1d0/beep0 and p1d1/beep1 pins in the general-purpose output port mode or beep output mode by using the beep/general-purpose port pin function selection register. figure 19-2 shows the configuration of the port 1d bit i/o selection register. figure 19-3 shows the configuration of the beep/general-purpose port pin function selection registerion. figure 19-2. configuration of port 1d bit i/o selection register name flag symbol b 3 p 1 d b i o 3 b 2 p 1 d b i o 2 b 1 p 1 d b i o 1 b 0 p 1 d b i o 0 address (bank15) 6ch read/write r/w port 1d bit i/o selection power-on reset wdt&sp reset ce reset clock stop at reset 0 1 0 0 0 0 0 0 0 0 0 1 sets p1d0/beep0 pin in input mode sets p1d0/beep0 pin in output mode. selects input or output port mode sets p1d1/beep1 pin in input mode sets p1d1/beep1 pin in output mode selects input or output port mode sets p1d2 pin in input mode sets p1d2 pin in output mode selects input or output port mode sets p1d3 pin in input mode sets p1d3 pin in output mode selects input or output port mode 0 1 0 1 retained retained
338 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 19-3. configuration of beep/general-purpose port pin function selection register name flag symbol b 3 0 b 2 0 b 1 b e e p 1 s e l b 0 b e e p 0 s e l address 13h read/write r/w beep/general-purpose port pin function selection power-on reset wdt&sp reset ce reset clock stop at reset 000 0 0 0 0 0 0 0 0 1 uses p1d0/beep0 pin as general-purpose i/o port uses p1d0/beep0 pin for beep selects general-purpose i/o port or beep uses p1d1/beep1 pin as general-purpose i/o port uses p1d1/beep1 pin for beep selects general-purpose i/o port or beep fixed to 0 0 1
339 pd17717, 17718, 17719 data sheet u12330ej2v0ds 19.3 clock selection block and clock generation block the clock selection block selects the output frequency of beep1 and beep0 by using the beep clock selection register. the clock generation block generates the clock to be output to beep0 and beep1. the clock frequency generated is 1 khz, 3 khz, 4 khz, 6.7 khz, 67 hz, or 200 hz. figure 19-4. configuration of beep clock selection register name flag symbol b 3 b e e p 1 c k 1 b 2 b e e p 1 c k 0 b 1 b e e p 0 c k 1 b 0 b e e p 0 c k 0 address 14h read/write r/w beep clock selection power-on reset wdt&sp reset ce reset clock stop at reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 khz 3 khz 4 khz 6.7 khz sets output frequency of beep0 4 khz 3 khz 200 hz 67 hz sets output frequency of beep1 0 0 1 1 0 1 0 1 0 0 1 1
340 pd17717, 17718, 17719 data sheet u12330ej2v0ds 19.4 output waveform of beep the duty factor of the beep output waveform is 50%. example f = 3 khz f = 1 khz f = 200 hz f: output frequency of beep 166.7 s 166.7 s 500 s 2.5 ms 2.5 ms 500 s 19.5 status at reset 19.5.1 at power-on reset the p1d0/beep0 and p1d1/beep1 pins are set in the general-purpose input port mode. 19.5.2 at wdt&sp reset the p1d0/beep0 and p1d1/beep1 pins are set in the general-purpose input port mode. 19.5.3 on execution of clock stop instruction the p1d0/beep0 and p1d1/beep1 pins are set in the general-purpose i/o port mode, and retain the previous input or output status. 19.5.4 at ce reset the p1d0/beep0 and p1d1/beep1 pins are set in the general-purpose i/o port mode, and retain the previous input or output status. 19.5.5 in halt status the previous status is retained.
341 pd17717, 17718, 17719 data sheet u12330ej2v0ds 20. standby the standby function is used to reduce the current consumption of the device while the device is backed up. 20.1 outline of standby function figure 20-1 outlines the standby block. the standby function reduces the current consumption of the device by partly or totally stopping the device operation. the following three types of standby functions are available for selection as the application requires. halt function clock stop function device operation control function by ce pin the halt function reduces the current consumption of the device by stopping the cpu operation by using a dedicated instruction halt h . the clock stop function reduces the current consumption of the device by stopping the oscillation of the oscillation circuit by using a dedicated instruction stop s . the ce pin can be said to be one of the standby functions because it can be used to control the operation of the pll frequency synthesizer and to reset the device. figure 20-1. outline of standby block interrupt control block btm0cy p0d3/ad3 p0d2/ad2 p0d1/ad1 p0d0/ad0 input latch oscillation circuit x out x in halt control circuit halt h clock stop control circuit stop s cpu program counter alu system register control register instruction decoder
342 pd17717, 17718, 17719 data sheet u12330ej2v0ds 20.2 halt function 20.2.1 outline of halt function the halt function stops the operating clock of the cpu by executing the halt h instruction. when this instruction is executed, the program is stopped until the halt status is later released. therefore, the current consumption of the device in the halt status is reduced by the operating current of the cpu. the halt status is released by using basic timer 0 carry ff, interrupt, or port input (p0d). the release condition is specified by operand h of the halt h instruction. 20.2.2 halt status in the halt status, all the operations of the cpu are stopped. in other words, execution of the program is stopped at the halt h instruction. however, the peripheral hardware units continue the operation specified before execution of the halt h instruction. for the operation of each peripheral hardware unit, refer to 20.4 device operation in halt and clock stop status . 20.2.3 halt release condition figure 20-2 shows the halt release condition. the halt release condition is specified by 4-bit data specified by operand h of the halt h instruction. the halt status is released when the condition specified by 1 in operand h . when the halt status is released, program execution is started from the instruction after the halt h instruction. if the halt status is released by an interrupt, the operation to be performed after the halt status has been released differs depending on whether the interrupts are enabled (ei status) or disabled (di status) when an interrupt source (irqxxx = 1) is issued with the interrupt (ipxxx = 1) enabled. if two or more releasing conditions are specified, the halt status is released when one of the specified condition is satisfied. if 0000b is set as halt release condition h , no releasing condition is set. if the device is reset (by means of power- on reset, wdt&sp reset, or ce reset) at this time, the halt status is released. figure 20-2. halt release condition operand halt h (4 bits) b 3 b 2 b 1 b 0 0 1 released when high level is input to port 0d released when basic timer 0 carry ff is set to 1 undefined (fix this bit to 0 .) released when interrupt is accepted not released even if condition is satisfied released if condition is satisfied sets halt status releasing condition
343 pd17717, 17718, 17719 data sheet u12330ej2v0ds 20.2.4 releasing halt by input port (p0d) the halt releasing condition using an input port is specified by the halt 0001b instruction. when the halt releasing condition using an input port is specified, the halt status is released if a high level is input to one of the p0d0 through p0d3 pins. the p0d0 through p0d3 pins are multiplexed with the a/d converter input pins ad0 through ad3, and the halt status is not released when these pins are used as a/d converter input pins. an example is given below. to use as key matrix the p0d0 through p0d3 pins are general-purpose input port pins which can be set in the input or output mode in 1-bit units and can be connected to an internal pull-down resistor. if connection of the internal pull-down resistor is specified by software, an external resistor can be eliminated as shown in this example (the internal- pull down resistor is connected at power-on reset). the halt 0001b instruction is executed after the general-purpose output ports for key source signal are made high. note that if an alternate switch is used as shown by switch a in the above figure, the halt status is released immediately because a high level is input to the p0d0/ad0 pin while switch a is closed. p0d3/ad3 p0dpld3 flag p0d2/ad2 p0d1/ad1 p0d0/ad0 switch a general-purpose output port latch
344 pd17717, 17718, 17719 data sheet u12330ej2v0ds 20.2.5 releasing halt status by basic timer 0 carry ff releasing the halt status by using the basic timer 0 carry ff is specified by the halt 0010b instruction. when releasing the halt status by the basic timer 0 carry ff is specified, the halt status is released as soon as the basic timer 0 carry ff has been set to 1. the basic timer 0 carry ff corresponds to the btm0cy flag on a one-to-one basis and is set at fixed time intervals (100, 50, 20, or 10 ms). therefore, the halt status can be released at fixed time intervals. example to release halt status every 100 ms to execute processing a hlttmr dat 0010b ; symbol definition initflg not btm0ck1, not btm0ck0 ; sets time interval of basic timer 0 to 100 ms loop: halt hlttmr ; specifies setting of basic timer 0 carry ff as halt releasing condition skt1 btmocy ; embedded macro br loop ; branches to loop if btm0cy flag is not set processing a ; executes processing a if carry occurs br loop 20.2.6 releasing halt status by interrupt releasing the halt status by an interrupt is specified by the halt 1000b instruction. when releasing the halt status by an interrupt is specified, the halt status is released as soon as the interrupt has been accepted. many interrupt sources are available as described in 12. interrupts. which interrupt source is used to release the halt status must be specified in advance in software. to accept an interrupt, each interrupt request must be issued from each interrupt source and each interrupt must be enabled (by setting the corresponding interrupt enable flag). therefore, the interrupt is not accepted even if the interrupt request is issued, and the halt status is not released. when the halt status is released by accepting an interrupt, the program flow branches to the vector address of the interrupt. when the reti instruction is executed after interrupt servicing, the program flow is restored to the instruction after the halt instruction. if all the interrupts are disabled (di status), the halt status is released by enabling an interrupt (ipxxx = 1) and issuing an interrupt source (irqxxx = 1), and the flow of the program goes to the instruction after the halt instruction.
345 pd17717, 17718, 17719 data sheet u12330ej2v0ds example releasing halt status by timer 0 and int0 pin interrupts in this example, the halt status is released and processing b is executed when timer 0 interrupt is accepted. and processing a is executed when int0 pin interrupt is accepted. each time the halt status has been released, processing c is executed. hltint dat 1000b ; symbol definition start: ; address 0000h br main ;*** interrupt vector address *** nop ; si03 nop ; si02 nop ; timer3 nop ; timer2 nop ; timer1 br inttm0 ; branches to timer 0 interrupt processing nop ; int4 nop ; int3 nop ; int2 nop ; int1 br int0 ; branches to int0 interrupt processing nop ; ce down edge int0: ; int0 pin interrupt vector address (000bh) processing a ; int0 pin interrupt processing ei reti intmm0: processing b ; timer 0 interrupt processing ei reti main: initflg not tmock1, tm0ck0 ; sets timer 0 count clock to 100 s mov dbf1, #0 mov dbf0, #0ah put tm0m,dbf ; sets time interval of timer 0 interrupt to 1 ms set2 tm0res, tm0en ; resets and starts timer 0 set2 iptm0, ip0 ; enables int0 and timer 0 interrupts loop: processing c ; main routine processing ei ; enables all interrupts halt hltint ; specifies releasing halt status by interrupt ;<1> br loop if the int0 pin interrupt request and timer 0 interrupt request are issued simultaneously in the halt status, processing a for the int0 pin, which has the higher hardware priority, is executed. after execution of processing a and when reti is executed, the program branches to the br loop instruction of <1>. however, the br loop instruction is not executed, and timer 0 interrupt is immediately accepted. when the reti instruction is executed after processing b of timer 0 interrupt has been executed, the br loop instruction is executed.
346 pd17717, 17718, 17719 data sheet u12330ej2v0ds caution to reset the interrupt request flag (irqxxx) once before the halt instruction is executed, insert a nop instruction (or one or more other instructions) between the halt instruction and the instruction that resets the interrupt request flag (irqxxx) as shown below. if a nop instruction (or one or more other instructions) is not inserted, the interrupt request flag is not reset, and therefore, the halt status is released immediately. example : : ; irqxxx is set at certain timing : clr1 irq ; resets irqxxx flag once nop ; resets irqxxx flag at this timing ; unless this period is missing, the irqxxx flag is not reset, ; and the next halt instruction is immediately released halt 1000b ;
347 pd17717, 17718, 17719 data sheet u12330ej2v0ds 20.2.7 if two or more releasing conditions are specified at same time if two or more halt releasing conditions are specified at same time, the halt status is released when one of the conditions is satisfied. the following program example shows how the releasing conditions are identified if two or more conditions are satisfied at the same time. example hltint dat 1000b hltbtm dat 0010b hltp0d dat 0001b p0d mem 0.73h start: br main ;*** interrupt vector address *** nop ; si03 nop ; si02 nop ; timer3 nop ; timer2 nop ; timer1 nop ; timer0 nop ; int4 nop ; int3 nop ; int2 nop ; int1 br int0 ; branches to int0 interrupt processing nop ; ce down edge int0: ; int0 pin interrupt vector address (000bh) processing a ; int0 pin interrupt processing ei reti btmoup: ; timer carry ff processing processing b ret p0dp: ; p0d input processing processing c ret main: initflg not btm0ck1, not btm0ck0 ; selects 100 ms as clock of basic timer 0 set1 ip0 ; enables int0 pin interrupt ei loop: halt hltint or hltbtm or hltp0c ; selects interrupt, timer carry ff, and p0d input as halt releasing conditions skf1 btm0cy ; detects btm0cy flag call btm0up ; timer carry ff processing if flag is set to 1 skf p0d, 1111b ; detects p0d input call p0dp ; port input processing if p0d is high br loop
348 pd17717, 17718, 17719 data sheet u12330ej2v0ds in the above example, three halt status releasing conditions, int0 pin interrupt, 100-ms basic timer 0 carry ff, and port 0d input, are specified. to identify which condition has released the halt status, a vector address (interrupt), btm0cy flag (timer carry ff), and port register (port input) are detected. to use two or more releasing conditions, the following two points must be noted. when the halt status is released, all the specified releasing conditions must be detected. the releasing condition with the higher priority must be detected first. 20.3 clock stop function 20.3.1 outline of clock stop function the clock stop function stops the oscillation circuit of a 4.5-mhz crystal resonator by executing the stop s instruction (clock stop status). therefore, the current consumption of the device is reduced to 30 a max. 20.3.2 clock stop status in the clock stop status, all the device operations of the cpu and peripheral hardware units are stopped because the generation circuit of the crystal resonator is stopped. for the operations of the cpu and peripheral hardware units, refer to 20.4 device operation in halt and clock stop status . in the clock stop status, the power failure detection circuit does not operate even if the supply voltage v dd of the device is raised to 2.2 v. therefore, the data memory can be backed up at a low voltage. for the power failure detection circuit, refer to 21. reset . 20.3.3 releasing clock stop status figure 20-3 shows the stop status releasing conditions. the stop status releasing condition is specified by 4-bit data specified by operand s of the stop s instruction. the stop status is released when the condition specified by 1 in operand s is satisfied. when the stop status has been released, a halt period which is half the time (t set /2) specified by the basic timer 0 clock selection register as oscillation circuit stabilization wait time has elapsed, and the program execution is started from the instruction next to the stop s instruction. if releasing the stop status by an interrupt is specified, however, the program operation after the stop status has been released differs depending on whether the interrupt is enabled (ei status) or disabled (di status) when an interrupt source is issued (irqxxx = 1) with the interrupt enabled (ipxxx = 1). if all the interrupts are enabled (ei status), the stop status is released when the interrupt is enabled (ipxxx = 1) and the interrupt source is issued (irqxxx = 1), and the program flow returns to the instruction next to the stop instruction. if all the interrupts are disabled (di status), the stop status is released when the interrupt is enabled (ipxxx = 1) and the interrupt resource is issued (irqxxx = 1), and the program flow returns to the instruction next to the stop instruction. if two or more releasing conditions are specified at one time, and if one of the conditions is satisfied, the stop status is released. if 0000b is specified as stop releasing condition s , no releasing condition is satisfied. if the device is reset at this time (by means of power-on reset, or ce reset), the stop status is released.
349 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 20-3. stop releasing conditions operand stop s (4 bits) b 3 b 2 b 1 b 0 0 1 releases when high level is input to port 0d undefined (fix this bit to 0 .) undefined (fix this bit to 0 .) released by interrupt of falling edge of int0 through int4 pins and ce pin not released even if condition is statisfied released if condition is satisfied specifies stop status releasing condition the stop s instruction is executed as a nop instruction when the ce pin rises and when the ce reset counter operates. the operating status of the ce reset counter can be detected by the cecntstt flag (for the ce reset counter, refer to 21. reset ). 20.3.4 releasing clock stop status by high level input of port 0d figure 20-4 illustrates how the clock stop status is released by the high level input to port 0d. figure 20-4. releasing clock stop status by high level input of port 0d v dd p0d x out 5 v 0 v h l 2.2 v stop s instruction starts from instruction next to stop s oscillation stops t set /2 halt period t set : basic timer 0 setting time 20.3.5 cautions on releasing clock stop status for the cautions on releasing the clock stop status, refer to (2) releasing from clock stop status in 21.4.4 cautions on raising supply voltage v dd .
350 pd17717, 17718, 17719 data sheet u12330ej2v0ds 20.4 device operation in halt and clock stop status table 20-1 shows the operations of the cpu and peripheral hardware units in the halt and clock stop status. in the halt status, all the peripheral hardware units continue the normal operation until instruction execution is stopped. in the clock stop status, all the peripheral hardware units stop operation. the control registers that control the operations of the peripheral hardware units operate normally (not initialized) in the halt status, but are initialized to specified values when the clock stop instruction is executed. in other words, all peripheral hardware continues the operation specified by the control register in the halt status, and the operation is determined by the initialized value of the control register in the clock stop status. for the values of the control registers in the clock stop status, refer to 8. register file (rf) . table 20-1. device operation in halt and clock stop status peripheral hardware status halt clock stop program counter stops at address of halt instruction stops at address of stop instruction system register retained retained peripheral register retained partly initialized note 1 control register retained partly initialized note 1 timer normal operation operation stops pll frequency synthesizer normal operation note 2 operation stops a/d converter normal operation operation stops d/a converter normal operation stops operation and used as general- purpose output port serial interface stops operation when internal clock (master) stops operation and used as general- is selected and continues operation when purpose i/o port external clock (slave) is selected frequency counter normal operation stops operation and used as general- purpose input port beep output normal operation stops operation and used as general- purpose i/o port general-purpose i/o port normal operation retained general-purpose input port normal operation input port general-purpose output port normal operation retains output latch notes 1. for the value to which these registers are initialized, refer to 5. system register (sysreg) and 8. register file (rf) . 2. the pll frequency synthesizer is automatically disabled by the low level input to the ce pin. 20.5 cautions on processing of each pin in halt and clock stop status the halt status is used to reduce the current consumption when, say, only the watch is used. the clock stop function is used to reduce the current consumption of the device to only use the data memory. therefore, the current consumption must be reduced as much as possible in the halt status or clock stop status. at this time, the current consumption significantly varies depending on the status of each pin, and the points shown in table 20-2 must be noted.
351 pd17717, 17718, 17719 data sheet u12330ej2v0ds table 20-2. status of each pin in halt and clock stop status and cautions (1/2) pin function pin symbol status of each pin and cautions on processing halt status clock stop status general- port 0a p0a3/sda purpose p0a2/scl i/o port p0a1/sck2 p0a0/so2 port 0b p0b3/si2 p0b2/sck3 p0b1/so3/txd p0b0/si3/rxd port 0c p0c3-p0c0 port 1d p1d3 p1d2 p1d1/beep1 p1d0/beep0 port 2a p2a2 p2a1/fcg1 p2a0/fcg0 port 2b p2b3-p2b0 port 2c p2c3-p2c0 port 2d p2d2/sck p2d1/sb1 p2d0/sb0 port 3a p3a3-p3a0 port 3b p3b3-p3b0 port 3c p3c30p3c0 port 3d p3d3-p3d0 general- port 0d p0d3/ad3 purpose | input port p0d0/ad0 port 1a p1a3/int4 p1a2/int3 p1a1 p1a0/tm0g port 1c p1c3/ad5 p1c2/ad4 p1c1/amifc p1c0/fmifc general- port 1b p1b3 purpose p1b2/pwm2 output port | p1b0/pwm0 retains status before halt (1) when specified as output pin current consumption increases if pin is externally pulled down while it outputs high level, or externally pulled up while it outputs low level. exercise care in using n-ch open-drain output (p0a3, p0a2, p1b3 through p1b0, p2d1, p2d0) (2) when specified as input pin current consumption increases due to noise if pin is floated (3) port 0d (p0d3/ad3 through p0d0/ ad0) current consumption increases if pin is externally pulled up because it is provided with pull-down resistor selectable by software (4) port 1c (p1c3/ad5, p1c2/ad4, p1c1/amifc, p1c0/fmifc) when p1c1/amifc or p1c0/fmifc pin is used for if counter, current consumption increases because internal amplifier operates all port pins are set in general-purpose port mode (except p0d3/ad3 through p0d0/ad0, p1a3/int4, p1a2/int3, p1c3/ad5, and p1c2/ad4) input or output mode of general-purpose i/o port set before clock stop status is retained. (1) when specified as general-purpose output port current consumption increases due to noise if pin is floated (2) when specified as general-purpose input port current consumption does not increase due to noise even if pin is floated (3) p1a3/int4, p1a2/int3 set as interrupt pin and current consumption increases due to external noise if pin is floated (4) p0d3/ad3 through p0d0/ad0, p1c3/ad5, p1c2/ad4 pin used for a/d converter is retained as is. pull-down resistor of p0d3 through p0d0 pin retains previous status specified as general-purpose output port. output contents are retained as is. if pin is externally pulled down while it outputs high level or externally pulled up while it outputs low level, current consumption increases
352 pd17717, 17718, 17719 data sheet u12330ej2v0ds table 20-2. status of each pin in halt and clock stop status and cautions (2/2) pin function pin symbol status of each pin and cautions on processing halt status clock stop status external interrupt int4-int0 current consumption increases due to noise if pin is floated pll frequency vcol synthesizer vcoh eo0 eo1 crystal oscillation x in circuit x out 20.6 device operation control function of ce pin the ce pin controls the following functions by the input level and rising edge of the signal input from an external source. pll frequency synthesizer interrupt by falling edge of ce pin resetting of device 20.6.1 controlling operation of pll frequency synthesizer the pll frequency synthesizer can operate only when the ce pin is high. it is automatically disabled when the ce pin is low. when the synthesizer is disabled, the vcoh and vcol pins are internally pulled down, and the eo0 and eo1 pins are floated. for details, refer to 17.5 pll disabled status . the pll frequency synthesizer can be disabled in software even when the ce pin is high. 20.6.2 controlling interrupt by falling edge input of ce pin an interrupt can be generated by the falling edge of the ce pin. for details, refer to 12. interrupts . current consumption increases during pll operation. when pll is disabled, pin is in following status: vcoh, vcol : internally pulled down eo1, eo0 : floated pll is automatically disabled if ce pin goes low pll is disabled vcoh, vcol : internally pulled down eo1, eo0 : floated current consumption changes due to oscillation waveform of crystal oscillation circuit. the higher oscillation amplitude, the lower current consumption. oscillation amplitude must be evaluated because it is influenced by crystal resonator or load capacitor used x in pin is internally pulled down, and x out pin outputs high level
353 pd17717, 17718, 17719 data sheet u12330ej2v0ds 20.6.3 resetting device the device can be reset (ce reset) by raising the ce pin. the device can also be reset as follows: power-on reset on application of supply voltage v dd watchdog timer reset for software hang-up detection and stack overflow/underflow reset reset by reset pin for details, refer to 21. reset . 20.6.4 signal input to ce pin the ce pin does not accept a low level or high level of less than 167 s to prevent malfunctioning due to noise. the level of the signal input to the ce pin can be detected by the ce pin status detection flag of the ce pin interrupt request register (rf address 3fh). figure 20-5 shows the relationship between the input signal and ce flag. figure 20-5. relationship between input signal of ce pin and ce flag ce pin ce flag h l 1 0 less than 167 s 167 s pll can operate pll disabled pll disabled note ce reset is effected in synchronization with next basic timer 0 carry ff (when ce reset count register is 1 ) less than 167 s 167 s ce reset note unless the pll mode selection register and pll reference frequency selection register are rewritten by software, the pll disabled status is retained.
354 pd17717, 17718, 17719 data sheet u12330ej2v0ds 20.6.5 configuration and function of ce pin interrupt request register the ce pin interrupt request register detects the input signal level of the ce pin. figure 20-6 shows the configuration of the ce pin interrupt request register. figure 20-6. configuration of ce pin interrupt request register note irqce is a r/w flag. name flag symbol b 3 c e b 2 0 b 1 c e c n t s t t b 0 i r q c e address 3fh read/write r note ce pin interrupt request power-on reset wdt&sp reset ce reset clock stop at reset u u u u 00 0 0 0 0 0 r r 0 1 no interrupt request interrupt request sets interrupt request issuance status of ce pin stops operates detects status of ce reset counter low level is input high level is input detects status of ce pin fixed to 0 0 1 0 1 u: undefined r: retained
355 pd17717, 17718, 17719 data sheet u12330ej2v0ds 21. reset 21.1 outline of reset the reset function is used to initialize the device. the pd17719 can be reset in the following ways: ce reset power-on reset reset by reset pin wdt&sp reset figure 21-1. configuration of reset block x out x in v dd reset ce stop s instruction voltage detection circuit falling detection circuit rising detection circuit btm0cy flag read power failure detection block timer ff block divider selector basic timer 0 carry r s q basic timer 0 carry disable ff power-on clear signal (poc) reset control circuit stop instruction ce reset timer carry counter watchdog timer stack overflow/underflow detection block ce reset signal wdt&sp reset signal
356 pd17717, 17718, 17719 data sheet u12330ej2v0ds 21.2 ce reset ce reset is effected by raising the ce pin. when the ce pin goes high, the next rising edge of the basic timer 0 carry ff setting pulse is counted. when the count value coincides with the value set to the ce reset timer carry counter register (1 to 15 counts), the reset signal is generated. when ce reset is effected, the program counter, stack, system registers, and some of the control registers are initialized to the initial values, and program execution is started from address 0000h. for the initial value of each register, refer to the description of each register . figure 21-2. configuration of ce reset timer carry counter register name flag symbol b 3 c e c n t 3 b 2 c e c n t 2 b 1 c e c n t 1 b 0 c e c n t 0 address 06h read/write r/w ce reset timer carry counter power-on reset wdt&sp reset ce reset clock stop at reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 setting prohibited 1 count 2 counts 3 counts 4 counts 5 counts 6 counts 7 counts 8 counts 9 counts 10 counts 11 counts 12 counts 13 counts 14 counts 15 counts sets number of counts of timer carry counter for ce reset 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 retained retained
357 pd17717, 17718, 17719 data sheet u12330ej2v0ds the operation of ce reset differs depending on whether the clock stop instruction is used or not. this difference is described in 21.2.1 and 21.2.2 below. 21.2.3 describes the points to be noted when ce reset is effected. 21.2.1 ce reset without clock stop (stop s) instruction figure 21-2 shows the operation. when the ce pin has gone high, the ce reset timer carry counter starts counting at the rising edge of the basic timer 0 carry ff setting pulse. figure 21-3. ce reset operation without clock stop instruction (1/2) (a) normal operation when ? is set to ce reset timer carry counter when ? is set to ce reset timer carry counter v dd ce x out btm0cy flag setting pulse ce reset timer carry counter set value of ce reset timer carry counter ce reset signal ce reset 5 v 0 v h l h l h l h l h h l l t set 01 0 1 v dd ce x out btm0cy flag setting pulse ce reset timer carry counter set value of ce reset timer carry counter ce reset signal 5 v 0 v h l h l h l h l h h l l t set 0123n 2n 1 n 0 n ce reset
358 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 21-3. ce reset operation without clock stop instruction (2/2) (b) if status of ce pin changes while ce counter operates at this time, the ce reset timer carry counter status is not affected. 21.2.2 ce reset with clock stop (stop s) instruction used figure 21-4 shows the operation. when the clock stop instruction is used, the clock stop signal is output when the stop s instruction is executed, and oscillation is stopped and the device operation is stopped. when the ce pin goes high, the clock stop status is released, and oscillation is started (high level input of p0d or int pin interrupt can also be used as the clock stop status releasing conditions. for details, refer to 20. standby ). if the basic timer 0 carry ff setting pulse goes high after the ce pin has gone high, the halt status is released, and program execution is started from address 0 (ce reset). as the set time (t set ) of the basic timer 0 carry ff setting pulse, the value immediately before the clock stop instruction is executed is retained. because the set value of the ce reset timer carry counter is initialized to 1, ce reset is effected t set /2 after the ce pin has gone high. v dd ce x out btm0cy flag setting pulse ce reset timer carry counter set value of ce reset timer carry counter ce reset signal 5 v 0 v h l h l h l h l h h l l t set 0123n 2n 1 n 0 n ce reset
359 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 21-4. ce reset operation with clock stop instruction 21.2.3 cautions on ce reset because ce reset is effected regardless of the instruction under execution, the following points (1) and (2) must be noted. (1) time to execute timer processing such as watch when creating a watch program by using the basic timer 0 carry, the processing time of the program must be kept to within a specific time. for details, refer to 13.2.6 cautions on using basic timer 0 . (2) processing of data and flags used in program exercise care in rewriting the data and flags whose contents must not be changed even when ce reset is effected, such as security code. an example is shown below. v dd ce x out btm0cy flag setting pulse ce reset timer carry counter set value of ce reset timer carry counter normal operation 5 v 0 v h l h l h l h l h h l l t set n1 1 0 clock stop status halt status t set /2 stop s instruction clock stop status released. oscillation starts ce reset program execution starts from address 0 ce reset signal
360 pd17717, 17718, 17719 data sheet u12330ej2v0ds example 1. r1 mem 0.01h ; 1st digit of key input data of security code r2 mem 0.02h ; 2nd digit of key input data of security code r3 mem 0.03h ; 1st digit data when security code is changed r4 mem 0.04h ; 2nd digit data when security code is changed m1 mem 0.11h ; 1st digit of current security code m2 mem 0.12h ; 2nd digit of current security code start: key input processing r1 contents of key a ; security code input wait mode r2 contents of key b ; substitutes contents of pressed key to r1 and r2 set2 cmp, z ; <1> ; compares security code and input data sub r1, m1 sub r2, m2 skt1 z br error ; input data differs from security code main: key input processing r3 contents of key c ; security code rewriting mode r4 contents of key d ; substitutes contents of pressed key to r3 and r4 st m1, r3 ; <2> ; rewrites security code st m2, r4 ; <3> br main error: must not operate suppose the security code is 12h in the program in example 1. the contents of data memory addresses m1 and m2 are 1h and 2h , respectively. if ce reset is effected, the contents of key input and security code 12h are compared in <1>. if the two are the same, the normal processing is performed. if the security code is changed in the main processing, the new code is written to m1 and m2 in <2> and <3>. suppose the security code is changed to 34h . then 3h and 4h are written to m1 and m2 in <2> and <3>. if ce reset is effected as soon as <2> has been executed, program execution is started from address 0000h, without <3> being executed. consequently, the security code is set to 32h , making it impossible to clear the security system. in this case, create the program shown in example 2.
361 pd17717, 17718, 17719 data sheet u12330ej2v0ds example 2. r1 mem 0.01h ; 1st digit of key input data of security code r2 mem 0.02h ; 2nd digit of key input data of security code r3 mem 0.03h ; 1st digit data when security code is changed r4 mem 0.04h ; 2nd digit data when security code is changed m1 mem 0.11h ; 1st digit of current security code m2 mem 0.12h ; 2nd digit of current security code change flg 0.13h.0 ; 1 while security code is changed start: key input processing r1 contents of key a ; security code input wait mode r2 contents of key b ; substitutes contents of pressed key to r1 and r2 skt1 change ; <4> ; if change flag is 1 br security_chk st m1, r3 ; rewrites m1 and m2 st m2, r4 clr1 change security_chk: set2 cmp, z ; <1> ; compares security code and input data sub r1, m1 sub r2, m2 skt1 z br error ; input data differs from security code main: key input processing r3 contents of key c ; security code rewriting mode r4 contents of key d ; substitutes contents of pressed key to r3 and r4 set1 change ; <5> ; until security code is changed, ; sets change flag to 1 st m1, r3 ; <2> ; rewrites security code st m2, r4 ; <3> clr1 change ; if security code has been changed, ; sets change flag to 0 br main error: must not operate the program in example 2 sets the change flag to 1 in <5> before the security code is rewritten in <2> and <3>. therefore, even if ce reset is effected before <3> is executed, the security code is rewritten in <4>.
362 pd17717, 17718, 17719 data sheet u12330ej2v0ds 21.3 power-on reset power-on reset is effected by raising the supply voltage v dd of the device from a specific level (called a power- on clear voltage). if supply voltage v dd is lower than the power-on clear voltage, a power-on clear signal (poc) is output from the voltage detection circuit shown in figure 21-1. when the power-on clear signal is input to the reset control circuit, the crystal oscillation circuit is stopped and consequently, the device operation is stopped. at this time, the program counter, stack, system registers, and control registers are initialized (for the initial value, refer to the description of each register ). if supply voltage v dd exceeds the power-on clear voltage, the power-on clear signal is deasserted, crystal oscillation is started, and the device waits for release of the halt status by the basic timer 0 carry which has been initialized to 100 ms. program execution is started from address 0 at the rising edge of the basic timer 0 carry ff setting signal 50 ms after the supply voltage has exceeded the power-on clear voltage. normally, the power-on clear voltage is 3.5 v, but it is 2.2 v in the clock stop status. the operations of power-on reset are described in 21.3.1 and 21.3.2. the operation when supply voltage v dd is raised from 0 v is described in 21.3.3. caution although it is stated that the normal power-on clear voltage is 3.5 v (max.) and that in the clock stop status is 2.2 v (max.), the actual power-on clear voltage does not exceed these maximum values. figure 21-5. operation of power-on reset v dd ce power-on clear signal x out btm0cy flag setting pulse 5 v 0 v h l h l h h l l power-on clear voltage power-on clear released oscillation starts program starts from address 0 50 ms halt status device operation stops normal operation
363 pd17717, 17718, 17719 data sheet u12330ej2v0ds 21.3.1 power-on reset during normal operation figure 21-6 (a) shows the operation. as shown, the power-on clear signal is output and the device operation is stopped if the supply voltage v dd drops below 3.5 v, regardless of the input level of the ce pin. if v dd rises beyond 3.5 v again, program execution starts from address 0000h after a halt of 50 ms. normal operation means operation without the clock stop instruction, and includes the halt status set by the halt instruction. 21.3.2 power-on reset in clock stop status figure 21-6 (b) shows the operation. as shown, the power-on clear signal is output and the device operation is stopped when supply voltage v dd drops below 2.2 v. however, it does not appear that device operation has changed because the device is in the clock stop status. if v dd rises beyond 3.5 v, program execution starts from address 0000h after a halt of 50 ms. 21.3.3 power-on reset when supply voltage v dd rises from 0 v figure 21-6 (c) shows the operation. as shown, the power-on clear signal is output until supply voltage v dd rises from 0 v to 3.5 v. when v dd exceeds the power-on clear voltage, the crystal oscillation circuit starts operating, and program execution starts from address 0000h after a half of 50 ms.
364 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 21-6. power-on reset and supply voltage v dd (a) normal operation (including halt status) v dd ce power-on clear signal x out 5 v 3.5 v 0 v h l h l h l power-on clear voltage normal operation device operation stops halt status 50 ms power-on clear released oscillation starts program starts from address 0 (c) if supply voltage v dd rises from 0 v (b) in clock stop status v dd ce power-on clear signal x out 5 v 3.5 v 0 v h l h l h l power-on clear voltage device operation stops halt status 50 ms power-on clear released oscillation starts program starts from address 0 v dd ce power on clear signal x out 5 v 3.5 v 2.2 v 0 v h l h l h l power-on clear voltage normal operation stop s instruction clock stop device operation stops halt status 50 ms power-on clear released oscillation starts program starts from address 0
365 pd17717, 17718, 17719 data sheet u12330ej2v0ds 21.4 relationship between ce reset and power-on reset on the first application of supply voltage v dd , power-on reset and ce reset are performed at the same time. the reset operations at this time are described in 21.4.1 through 21.4.3. 21.4.4 describes the points to be noted when raising supply voltage v dd . 21.4.1 if v dd pin and ce pin go high at the same time figure 21-7 (a) shows the operation. at this time, the program starts from address 0000h because of power-on reset. 21.4.2 if ce pin rises in forced halt status set by power-on reset figure 21-7 (b) shows the operation. at this time, the program starts from address 0000h because of power-on reset, in the same manner as 21.4.1. 21.4.3 if ce pin rises after power-on reset figure 21-7 (c) shows the operation. at this time, the program starts from address 0000h because of power-on reset, and the program starts from address 0000h again at the rising edge of the next basic timer 0 carry ff setting signal because of ce reset.
366 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 21-7. relationship between power-on reset and ce reset (a) when v dd and ce pin rise at the same time (b) if ce pin rises in halt status (c) if ce pin rises after power-on reset v dd ce btm0cy flag setting pulse 5 v 3.5 v 0 v h l h l power-on clear voltage opera- tion stops halt status 50 ms normal operation power-on reset program starts ce reset program starts (if ce reset timer carr y counter is set to 1 ) v dd ce btm0cy flag setting pulse 5 v 3.5 v 0 v h l h l power-on clear voltage opera- tion stops halt status 50 ms normal operation power-on reset program starts v dd ce btm0cy flag setting pulse 5 v 3.5 v 0 v h l h l power-on clear voltage opera- tion stops halt status 50 ms normal operation power-on reset program starts
367 pd17717, 17718, 17719 data sheet u12330ej2v0ds 21.4.4 cautions on raising supply voltage v dd the following points (1) and (2) must be noted when raising supply voltage v dd . (1) to raise supply voltage v dd from level lower than power-on clear voltage supply voltage v dd must be raised once to a level higher than 3.5 v. figure 21-8 illustrates this. as shown in the figure, if a voltage less than 3.5 v is applied on application of v dd in a program that backs up v dd at 2.2 v by using the clock stop instruction, the power-on clear signal remains output, and the program is not executed. at this time, the output ports of the device output undefined values, increasing the current consumption in some cases. consequently, the backup time when the device is backed up by batteries is substantially shortened. figure 21-8. cautions on raising v dd v dd btm0cy flag setting pulse x out 5 v 3.5 v 2.2 v 0 v h l h l power-on clear signal h l power-on clear voltage operation stops halt status 50 ms because output ports are undefined during this period, current consumption may increase. power-on reset pro g arm starts opera- tion stops normal operation back up initialize during this period and then execute clock stop instruction stop s instruction
368 pd17717, 17718, 17719 data sheet u12330ej2v0ds (2) releasing from clock stop status if the device is released from the backup status when supply voltage v dd is backed up at 2.2 v by using the clock stop status, v dd must be raised to 3.5 v or more within t set /2 after the clock stop status has been released by int pin interrupt or high level input to port 0d. as shown in figure 21-9, the device is released from the clock stop status by means of ce reset. however, because the power-on clear voltage is changed to 3.5 v t set /2 after the clock stop status has been released, power-on reset is effected unless v dd is 3.5 v or higher. the same applies when v dd is raised. figure 21-9. releasing from clock stop status p0d btm0cy flag setting pulse x out 5 v 3.5 v 2.2 v 0 v 0 v h l h l power-on clear signal h l power-on clear voltage backup in clock stop status halt status t set /2 power-on clear voltage changes to 3.5 v at this point. therefore, v dd must be 3.5 v or higher before this point. normal operation backup stop s instruction h v dd program starts power-on clear voltage changes to 2.2 v at this point. therefore, v dd must be 3.5 v or higher before this point. t set : basic timer 0 setting time
369 pd17717, 17718, 17719 data sheet u12330ej2v0ds 21.5 reset by reset pin the device is reset by the reset pin in the following cases: to reset the device at voltage higher than power-on clear voltage external reset input in case of software hang-up caution if reset is executed by using the reset pin during program execution, the data of the data memory may be destroyed. therefore, exercise care when executing reset by using the reset pin. the reset operation is the same as that performed at power-on reset. when a low level is input to the reset pin, an internal reset signal is generated, the crystal oscillation circuit is stopped, and the device stops operation. at this point, the program counter, stack, system registers, and control registers are initialized (for the initial value, refer to the description of each register ). when the reset pin is raised next time, the crystal oscillation is started, and the device waits to be released from the halt wait status by the basic timer 0 carry which has been initialized to a 100-ms cycle. the program starts from address 0 at the rising edge of the basic timer 0 carry ff setting signal 50 ms after a high level has been input to the reset pin. because the pd17719 has a power-on reset function, connect the reset pin to v dd via resistor if the reset pin is not used for the above application. figure 21-10. reset operation by reset pin v dd reset x out btm0cy flag setting pulse 5 v 0 v h l h l h l device opeation stops halt status 50 ms oscillation starts program starts from address 0
370 pd17717, 17718, 17719 data sheet u12330ej2v0ds 21.6 wdt&sp reset wdt&sp reset includes the following: watchdog timer reset stack pointer overflow/underflow reset figure 21-11. outline of wdt&sp reset 21.6.1 watchdog timer reset the watchdog timer is a circuit that generates a reset signal when the execution sequence of the program is abnormal (hung-up). hanging-up means that the program jumps to an unexpected routine due to external noise, entering a specific infinite loop and causing the system to be deadlocked. by using the watchdog timer, the program can be restored from this hang-up status because a reset signal is generated from the watchdog timer at fixed time intervals and program execution is started from address 0. the watchdog timer does not function in the clock stop mode and halt mode. resetting by the watchdog timer initializes all the registers except the stack overflow selection register, watchdog timer counter reset register, basic timer 0 carry register, and ce reset timer carry counter. the watchdog timer reset is detected by the wdtcy flag (r&reset). instruction count clock 65536 instruction counter 131072 instruction counter stack overflow/under flow reset detection circuit wdtres aspres fla g ispres fla g wdtck1 flag wdtck0 falg wdtcy flag wdt&sp reset signal
371 pd17717, 17718, 17719 data sheet u12330ej2v0ds 21.6.2 watchdog timer setting flags these flags can be set only once after power-on reset on power application or reset by the reset pin. the wdtck0 and wdtck1 flags select an interval at which the reset signal is output. the reference time can be selected to the following three conditions: 655356 instructions 131072 instructions watchdog timer not set on power application, 131072 instructions are selected. if the reset signal generation interval is specified to be 131072 instructions, the watchdog timer ff must be reset at intervals not exceeding 131072 instructions. the valid reset period is from 1 to 131071 instructions. if the reset signal generation interval is 65536 instructions, the watchdog timer ff must be reset at intervals not exceeding 65536 instrutions. the valid reset period is from 1 to 65535 instructions. figure 21-12. configuration of watchdog timer clock selection register name flag symbol b 3 0 b 2 0 b 1 w d t c k 1 b 0 w d t c k 0 address 02h read/write r/w note watchdog timer clock selection power-on reset wdt&sp reset ce reset clock stop at reset 0011 0 1 0 1 does not set watchdog timer 65536 instructions setting prohibited 131072 instructions selects clock of watchdog timer fixed to 0 0 0 1 1 retained retained retained note can be written only once.
372 pd17717, 17718, 17719 data sheet u12330ej2v0ds the wdtres flag is used to reset the watchdog timer counter. when this flag is set to 1, the watchdog timer counter is automatically reset. if the wdtres flag is set to 1 once within a reference time in which the wdtck0 and wdtck1 flags are set, the reset signal is not output by the watchdog timer. figure 21-13. configuration of watchdog timer counter reset register name flag symbol b 3 w d t r e s b 2 0 b 1 0 b 0 0 address 03h read/write w&reset watchdog timer counter reset power-on reset wdt&sp reset ce reset clock stop at reset u u u u 000 0 1 invalid resets watchdog timer counter resets watchdog timer counter fixed to 0 u: undefined
373 pd17717, 17718, 17719 data sheet u12330ej2v0ds 21.6.3 stack pointer overflow/underflow reset a reset signal is generated if the address or interrupt stack overflows or underflows. stack pointer overflow/underflow reset can be used to detect a program hang-up in the same manner as watchdog timer reset. the reset signal is generated under the following conditions: interrupt due to overflow or underflow of interrupt stack (4 levels) interrupt due to overflow or underflow of address stack (15 levels) reset by stack pointer overflow or underflow initializes all the registers, except the stack overflow selection register, watchdog timer counter reset register, basic timer 0 carry register, and ce reset timer carry counter. generation of stack pointer overflow or underflow reset is detected by the wdtcy flag (r&reset). 21.6.4 stack pointer setting flag the stack overflow/underflow reset selection register can be set only once after power-on reset on power application or reset by the reset pin. this register specifies whether reset by address stack overflow or underflow and reset by interrupt stack overflow or underflow are enabled or disabled.
374 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 21-14. configuration of stack overflow/underflow reset selection register note can be written only once. name flag symbol b 3 0 b 2 0 b 1 i s p r e s b 0 a s p r e s address 05h read/write r/w note stack overflow/underflow reset selection power-on reset wdt&sp reset ce reset clock stop at reset 0011 0 1 disables reset enables reset selects address stack overflow/underflow reset disables reset enables reset selects interrupt stack overflow/underflow reset fixed to 0 retained retained retained 0 1
375 pd17717, 17718, 17719 data sheet u12330ej2v0ds figure 21-15. configuration of wdt&sp reset selection register name flag symbol b 3 0 b 2 0 b 1 0 b 0 w d t c y address 16h read/write r&reset wdt&sp reset status detection power-on reset wdt&sp reset ce reset clock stop at reset 0000 1 r r 0 1 no reset request reset request detects occurrence of wdt&sp reset fixed to 0 r: retained
376 pd17717, 17718, 17719 data sheet u12330ej2v0ds 21.7 power failure detection power failure detection is used to identify whether the device has been reset by application of supply voltage v dd , reset pin, or ce pin. because the contents of the data memory and output ports are undefined on power application, these contents are initialized by using power failure detection. power failure detection can be performed in two ways: by detecting the btm0cy flag and the contents of the data memory (ram judgment). 21.7.1 and 21.7.2 describe the power failure detection circuit and power failure detection by using the btm0cy flag. 21.7.3 and 21.7.4 describe power failure detection by ram judgment method. figure 21-16. power failure detection flowchart program starts power failure detection not power failure power failure initializes data memory and output ports 21.7.1 power failure detection circuit the power failure detection circuit consists of a voltage detection circuit, and basic timer 0 carry disable flip-flop that is set by the output (power-on clear signal) of the voltage detection circuit, and timer carry, as shown in figure 21-1. the basic timer 0 carry disable ff is set to 1 by the power-on clear signal, and is reset to 0 when an instruction that reads the btm0cy flag is executed. when the basic timer 0 carry disable ff is set to 1, the btm0cy flag is not set to 1. if the power-on clear signal is output (at power-on reset), the program starts with the btm0cy flag reset. after that, the btm0cy flag is disabled from being set until an instruction that reads the flag is executed. once the instruction that reads this flag has been executed, the btm0cy flag is set each time the basic timer 0 carry ff setting pulse rises. therefore, by detecting the content of the btm0cy flag when the device is reset, whether the device has been reset by power-on reset (power failure) or ce reset (not power failure) can be identified. that is, the device has been reset by power-on reset if the btm0cy flag has been reset to 0. it has been reset by ce reset if the flag has been set to 1. because the voltage at which a power failure can be detected is the same as that at which power-on reset is executed, v dd = 3.5 v during crystal oscillation and v dd = 2.2 v in the clock stop status. the operation of the btm0cy flag is the same regardless of whether the device has been reset by the reset pin or by power-on reset.
377 pd17717, 17718, 17719 data sheet u12330ej2v0ds 21.7.2 cautions on detecting power failure by btm0cy flag the following points must be noted when counting the watch timer by using the btm0cy flag. (1) updating watch when creating a watch program using the timer carry, the watch must be updated after a power failure has been detected. this is because the btm0cy flag is reset to 0 because it is read after a power failure has been detected. as a result, counting of the watch is overlooked once. (2) watch updating processing time updating the watch must be completed before the next basic timer 0 carry ff setting pulse rises. this is because ce reset is executed before the watch updating processing has been completed if the ce pin goes high during watch updating processing. for the details of (1) and (2), refer to (3) compensating basic timer 0 carry at ce reset in 13.2.6 . the following points must be noted when performing processing in case of a power failure. (3) timing to detect power failure when counting the watch by using the btm0cy flag, the btm0cy flag must be read to detect a power failure before the next basic timer 0 carry ff setting pulse rises after the program has been started from address 0000h. this is because, if the basic timer 0 carry ff setting time is set to, say, 10 ms, and if the power failure is detected 11 ms after the program has been started, the btm0cy flag is overlooked once. for further information, refer to (3) compensating basic timer 0 carry at ce reset in 13.2.6 . power failure detection and initial processing must be performed within the time in which the basic timer 0 carry ff is set, as shown in the example below. this is because, if the ce pin rises and ce reset is executed during power failure processing or initial processing, the processing is stopped in midway, causing a problem. to update the basic timer 0 carry ff setting time in the initial processing, the instruction that changes the setting time must be executed at the end of the initial processing. this is because, if the basic timer 0 carry ff setting time is changed before the initial processing, the initial processing may not be executed to the end because ce reset may be executed.
378 pd17717, 17718, 17719 data sheet u12330ej2v0ds example start: ; program address 0000h ; <1> processing at reset ; <2> skt1 btm0cy ; power failure detection br initial backup: ; <3> watch updating br main initial: ; <4> initial processing ; <5> initflg btm0ck1, btm0ck0 ; embedded macro ; sets basic timer 0 carry ff ; sets time to 10 ms main: main processing skt1 btm0cy br main watch updating br main operation example (if ce reset timer counter is set to 1 ) v dd ce 10-ms pluse 50-ms pluse btm0cy flag setting pulse 5 v 0 v h l h l 50 ms 10 ms 50 ms <1> <4> <1> <3> <2> <2> power failure detection if processing time of <1> + <4> is longer than 100 ms, ce reset is executed in the middle of processing <4>. <5> ce reset power failure detection if processing time of <1> + <3> is too long, ce reset is executed. ce reset ce reset may be executed immediately depending on when the basic timer 0 carry ff setting time is changed. therefore, if <5> is executed before <4>, power failure processin g <4> ma y not be executed to the end.
379 pd17717, 17718, 17719 data sheet u12330ej2v0ds 21.7.3 power failure detection by ram judgment method by the ram judgment method, a power failure is detected by judging whether the contents of the data memory at a specific address are a specific value when the device has been reset. an example of a program that detects a power failure by ram judgment method is shown below. by the ram judgment method, a power failure is detected by comparing an undefined value and a specific value because the contents of the data memory are undefined on application of supply voltage v dd . therefore, a power failure may be judged by mistake by this method as described in 21.7.4 cautions on power failure detection by ram judgment method . example program example of power failure detection by ram judgment method m012 mem 0.12h m034 mem 0.34h m056 mem 0.56h m107 mem 1.07h m128 mem 1.28h m16f mem 1.6fh data0 dat 1010b data1 dat 0101b data2 dat 0110b data3 dat 1001b data4 dat 1100b data5 dat 0011b start: set2 cmp, z sub m012, #data0 ; if m012 = data0, and sub m034, #data1 ; m034 = data1, and sub m056, #data2 ; m056 = data2, and bank1 sub m107, #data3 ; m107 = data3, and sub m128, #data4 ; m128 = data4, and sub m16f, #data5 ; m16f = data5, bank0 skf1 z br backup ; branches to backup ; initial: initial processing mov m012, #data0 mov m034, #data1 mov m056, #data2 bank1 mov m107, #data3 mov m128, #data4 mov m16f, #data5 br main backup: backup processing main: main processing
380 pd17717, 17718, 17719 data sheet u12330ej2v0ds 21.7.4 cautions on power failure detection by ram judgment method because the values of the data memory on application of supply voltage v dd are basically undefined , the following points (1), (2), and (3) must be noted. (1) data to be compared where the number of bits of the data memory to be compared by the ram judgment method is n bits , the probability that the value of the data memory happens to coincide the value to be compared on application of v dd is (1/2) n . in other words, a power failure detected by the ram judgment method may be judged as backup at a probability of (1/2) n . to minimize this probability, compare as many bits as possible. because the contents of the data memory on application of v dd are likely to be the same value such as 0000b and 1111b , it is recommended that the data to be compared consist of a combination of 0 s and 1 s, such as 1010b and 0110b . (2) cautions on program if v dd rises from a level at which the contents of the data memory are destroyed as shown in figure 21-17, even if the value of the data memory to be compared is normal, the other parts of the data memory may be destroyed. if a power failure detection is performed by the ram judgment method at this time, it is judged to be a backup. therefore, the program must be designed so that a hang-up does not occur even if the contents of the data memory are destroyed. figure 21-17. v dd and destruction of data memory contents (3) cautions on reset pin if reset is executed by using the reset pin during program execution, the data of the data memory may be destroyed. therefore, exercise care when executing reset by using the reset pin. data memory destruction start voltage 5 v 0 v v dd values of data memor y addresses not used for ram j ud g ment ma y be destro y ed. data memory for ram judgment (normal) data memory
381 pd17717, 17718, 17719 data sheet u12330ej2v0ds 22. instruction set 22.1 outline of instruction set b 14 -b 11 b 15 01 bin hex 0000 0 add r,m add m,#n4 0001 1 sub r,m sub m, #n4 0010 2 addc r,m addc m,#n4 0011 3 subc r,m subc m,#n4 0100 4 and r,m and m,#n4 0101 5 xor r,m xor m,#n4 0110 6 or r,m or m,#n4 inc ar inc ix rorc r movt dbf,@ar push ar pop ar get dbf,p put p,dbf peek wr,rf poke rf,wr 0111 7 br @ar call @ar syscal entry ret retsk reti ei di stop s halt h nop 1000 8 ld r,m st m,r 1001 9 ske m,#n4 skge m,#n4 1010 a mov @r,m mov m,@r 1011 b skne m,#n4 sklt m,#n4 1100 c br addr (page 0) call addr (page 0) 1101 d br addr (page 1) mov m,#n4 1110 e br addr (page 2) skt m,#n4 1111 f br addr (page 3) skf m,#n
382 pd17717, 17718, 17719 data sheet u12330ej2v0ds 22.2 legend ar : address register asr : address stack register indicated by stack pointer addr : program memory address (low-order 11 bits) bank : bank register cmp : compare flag cy : carry flag dbf : data buffer entry : program memory address (bits 10 through 8, bits 3 through 0) entry h : program memory address (bits 10 through 8) entry l : program memory address (bits 3 through 0) h : halt release condition intef : interrupt enable flag intr : register automatically saved to stack when interrupt occurs intsk : interrupt stack register ix : index register mp : data memory row address pointer mpe : memory pointer enable flag m : data memory address indicated by m r , m c m r : data memory row address (high-order) m c : data memory column address (low-order) n : bit position (4 bits) n4 : immediate data (4 bits) page : page (bits 12 and 11 of program counter) pc : program counter p : peripheral address p h : peripheral address (high-order 3 bits) p l : peripheral address (low-order 4 bits) r : general register column address rf : register file address rf r : register file row address (high-order 3 bits) rf c : register file column address (low-order 4 bits) sgr : segment register (bit 13 of program counter) sp : stack pointer s : stop release condition wr : window register (x) : contents addressed by x
383 pd17717, 17718, 17719 data sheet u12330ej2v0ds 22.3 instruction list instructions mnemonic operand operation instruction code op code operand add add r,m (r) (r) + (m) 00000 m r m c r m,#n4 (m) (m) + n4 10000 m r m c n4 addc r,m (r) (r) + (m) + cy 00010 m r m c r m,#n4 (m) (m) + n4 + cy 10010 m r m c n4 inc ar ar ar + 1 00111 000 1001 0000 ix ix ix + 1 00111 000 1000 0000 subtract sub r,m (r) (r) (m) 00001 m r m c r m,#n4 (m) (m) n4 10001 m r m c n4 subc r,m (r) (r) (m) cy 00011 m r m c r m,#n4 (m) (m) n4 cy 10011 m r m c n4 logical or r,m (r) (r) v (m) 00110 m r m c r operation m,#n4 (m) (m) v n4 10110 m r m c n4 and r,m (r) (r) (m) 00100 m r m c r m,#n4 (m) (m) n4 10100 m r m c n4 xor r,m (r) (r) v (m) 00101 m r m c r m,#n4 (m) (m) v n4 10101 m r m c n4 judge skt m,#n cmp 0, if (m) n = n, then skip 11110 m r m c n skf m,#n cmp 0, if (m) n = 0, then skip 11111 m r m c n compare ske m,#n4 (m) n4, skip if zero 01001 m r m c n4 skne m,#n4 (m) n4, skip if not zero 01011 m r m c n4 skge m,#n4 (m) n4, skip if not borrow 11001 m r m c n4 sklt m,#n4 (m) n4, skip if borrow 11011 m r m c n4 rotate rorc r cy (r) b 3 (r) b 2 (r) b 1 (r) b 0 00111 000 0111 r transfer ld r,m (r) (m) 01000 m r m c r st m,r (m) (r) 11000 m r m c r mov @r,m if mpe = 1 : (mp, (r)) (m) 01010 m r m c r if mpe = 0 : (bank, m r , (r)) (m) m, @r if mpe = 1 : (m) (mp, (r)) 11010 m r m c r if mpe = 0 : (m) (bank, m r , (r)) m,#n4 (m) n4 11101 m r m c n4 movt dbf,@ar sp sp 1, asr pc, pc ar, 00111 000 0001 0000 dbf (pc), pc asr, sp sp + 1 push ar sp sp 1, asr ar 00111 000 1101 0000 pop ar ar asr, sp sp + 1 00111 000 1100 0000 get dbf,p dbf (p) 00111 p h 1011 p l put p,dbf (p) dbf 00111 p h 1010 p l peek wr,rf wr (rf) 00111 rf r 0011 rf c poke rf,wr (rf) wr 00111 rf r 0010 rf c v v v v
384 pd17717, 17718, 17719 data sheet u12330ej2v0ds instructions mnemonic operand operation instruction code op code operand branch br addr pc 10 0 addr, page 0 01100 addr pc 10 0 addr, page 1 01101 pc 10 0 addr, page 2 01110 pc 10 0 addr, page 3 01111 @ar pc ar 00111 000 0100 0000 subroutine call addr sp sp 1, asr pc 11100 addr pc 11 0, pc 10 0 addr @ar sp sp 1, asr pc 00111 000 0101 0000 pc ar syscal entry sp sp 1, asr pc, sgr 1 00111 entry h 0010 entry l pc 12, 11 0, pc 10 8 entry h , pc 7 4 0, pc 3 0 entry l ret pc asr, sp sp + 1 00111 000 1110 0000 retsk pc asr, sp sp + 1 and skip 00111 001 1110 0000 reti pc asr, intr intsk, sp sp + 1 00111 100 1110 0000 interrupt ei intef 1 00111 000 1111 0000 di intef 0 00111 001 1111 0000 others stop s stop 00111 010 1111 s halt h halt 00111 011 1111 h nop no operation 00111 100 1111 0000
385 pd17717, 17718, 17719 data sheet u12330ej2v0ds 22.4 assembler (ra17k) embedded macro instruction legend flag n : flg symbol n : bit number < > : can be omitted mnemonic operand operation n embedded sktn flag 1, ... flag n if (flag1) ~ (flag n) = all 1 , then skip 1 n 4 macro skfn flag 1, ... flag n if (flag 1) ~ (flag n) = all 0 , then skip 1 n 4 setn flag 1, ... flag n (flag 1) ~ (flag n) 11 n 4 clrn flag 1, ... flag n (flag 1) ~ (flag n) 01 n 4 notn flag 1, ... flag n if (flag n) = 0 , then (flag n) 11 n 4 if (flag n) = 1 , then (flag n) 0 initflg flag 1, if description = not flag n, then (flag n) 01 n 4 ... < flag n> if description = flag n, then (flag n) 1 bankn (bank) n0 n 15 expanded brx label jump label instruction callx function-name call sub-routine syscalx function-name or call system sub-routine expression initflgx flag 1, if description = not (or inv) n 4 ... flag n flag, (flag) 0 if description = flag, (flag) 1
386 pd17717, 17718, 17719 data sheet u12330ej2v0ds 23. reserved symbols 23.1 data buffer (dbf) symbol name attribute value r/w description dbf3 mem 0.0ch r/w bits 15 through 12 of data buffer dbf2 mem 0.0dh r/w bits 11 through 8 of data buffer dbf1 mem 0.0eh r/w bits 7 through 4 of data buffer dbf0 mem 0.0fh r/w bits 3 through 0 of data buffer 23.2 system registers (sysreg) symbol name attribute value r/w description ar3 mem 0.74h r/w bits 15 through 12 of address register ar2 mem 0.75h r/w bits 11 through 8 of address register ar1 mem 0.76h r/w bits 7 through 4 of address register ar0 mem 0.77h r/w bits 3 through 0 of address register wr mem 0.78h r/w window register bank mem 0.79h r/w bank register ixh mem 0.7ah r/w bits 10 through 8 of index register mph mem 0.7ah r/w bits 6 through 4 of memory pointer mpe flg 0.7ah.3 r/w memory pointer enable flag ixm mem 0.7bh r/w bits 7 through 4 of index register mpl mem 0.7bh r/w bits 3 through 0 of memory pointer ixl mem 0.7ch r/w bits 3 through 0 of index register rph mem 0.7dh r/w bits 6 through 3 of general register pointer rpl mem 0.7eh r/w bits 2 through 0 of general register pointer bcd flg 0.7eh.0 r/w bcd operation flag psw mem 0.7fh r/w program status word cmp flg 0.7fh.3 r/w compare flag cy flg 0.7fh.2 r/w carry flag z flg 0.7fh.1 r/w zero flag ixe flg 0.7fh.0 r/w index enable flag
387 pd17717, 17718, 17719 data sheet u12330ej2v0ds 23.3 port registers symbol name attribute value r/w description p0a3 flg 0.70h.3 r/w bit 3 of port 0a p0a2 flg 0.70h.2 r/w bit 2 of port 0a p0a1 flg 0.70h.1 r/w bit 1 of port 0a p0a0 flg 0.70h.0 r/w bit 0 of port 0a p0b3 flg 0.71h.3 r/w bit 3 of port 0b p0b2 flg 0.71h.2 r/w bit 2 of port 0b p0b1 flg 0.71h.1 r/w bit 1 of port 0b p0b0 flg 0.71h.0 r/w bit 0 of port 0b p0c3 flg 0.72h.3 r/w bit 3 of port 0c p0c2 flg 0.72h.2 r/w bit 2 of port 0c p0c1 flg 0.72h.1 r/w bit 1 of port 0c p0c0 flg 0.72h.0 r/w bit 0 of port 0c p0d3 flg 0.73h.3 r note bit 3 of port 0d p0d2 flg 0.73h.2 r note bit 2 of port 0d p0d1 flg 0.73h.1 r note bit 1 of port 0d p0d0 flg 0.73h.0 r note bit 0 of port 0d p1a3 flg 1.70h.3 r note bit 3 of port 1a p1a2 flg 1.70h.2 r note bit 2 of port 1a p1a1 flg 1.70h.1 r note bit 1 of port 1a p1a0 flg 1.70h.0 r note bit 0 of port 1a p1b3 flg 1.71h.3 r/w bit 3 of port 1b p1b2 flg 1.71h.2 r/w bit 2 of port 1b p1b1 flg 1.71h.1 r/w bit 1 of port 1b p1b0 flg 1.71h.0 r/w bit 0 of port 1b p1c3 flg 1.72h.3 r note bit 3 of port 1c p1c2 flg 1.72h.2 r note bit 2 of port 1c p1c1 flg 1.72h.1 r note bit 1 of port 1c p1c0 flg 1.72h.0 r note bit 0 of port 1c note these are input ports. however, even if an instruction that outputs data to these ports is described, the assembler and in-circuit emulator do not output an error message. moreover, nothing is affected in terms of operation even if such an instruction is actually executed on the device.
388 pd17717, 17718, 17719 data sheet u12330ej2v0ds symbol name attribute value r/w description p1d3 flg 1.73h.3 r/w bit 3 of port 1d p1d2 flg 1.73h.2 r/w bit 2 of port 1d p1d1 flg 1.73h.1 r/w bit 1 of port 1d p1d0 flg 1.73h.0 r/w bit 0 of port 1d p2a2 flg 2.70h.2 r/w bit 2 of port 2a p2a1 flg 2.70h.1 r/w bit 1 of port 2a p2a0 flg 2.70h.0 r/w bit 0 of port 2a p2b3 flg 2.71h.3 r/w bit 3 of port 2b p2b2 flg 2.71h.2 r/w bit 2 of port 2b p2b1 flg 2.71h.1 r/w bit 1 of port 2b p2b0 flg 2.71h.0 r/w bit 0 of port 2b p2c3 flg 2.72h.3 r/w bit 3 of port 2c p2c2 flg 2.72h.2 r/w bit 2 of port 2c p2c1 flg 2.72h.1 r/w bit 1 of port 2c p2c0 flg 2.72h.0 r/w bit 0 of port 2c p2d2 flg 2.73h.2 r/w bit 2 of port 2d p2d1 flg 2.73h.1 r/w bit 1 of port 2d p2d0 flg 2.73h.0 r/w bit 0 of port 2d p3a3 flg 3.70h.3 r/w bit 3 of port 3a p3a2 flg 3.70h.2 r/w bit 2 of port 3a p3a1 flg 3.70h.1 r/w bit 1 of port 3a p3a0 flg 3.70h.0 r/w bit 0 of port 3a p3b3 flg 3.71h.3 r/w bit 3 of port 3b p3b2 flg 3.71h.2 r/w bit 2 of port 3b p3b1 flg 3.71h.1 r/w bit 1 of port 3b p3b0 flg 3.71h.0 r/w bit 0 of port 3b p3c3 flg 3.72h.3 r/w bit 3 of port 3c p3c2 flg 3.72h.2 r/w bit 2 of port 3c p3c1 flg 3.72h.1 r/w bit 1 of port 3c p3c0 flg 3.72h.0 r/w bit 0 of port 3c p3d3 flg 3.73h.3 r/w bit 3 of port 3d p3d2 flg 3.72h.2 r/w bit 2 of port 3d p3d1 flg 3.73h.1 r/w bit 1 of port 3d p3d0 flg 3.73h.0 r/w bit 0 of port 3d
389 pd17717, 17718, 17719 data sheet u12330ej2v0ds 23.4 register file (control registers) symbol name attribute value r/w description sp mem 0.81h r/w stack pointer wdtck mem 0.82h r/w w atchdog timer clock selection flag (can be set only once after power application) wdtck1 flg 0.82h.1 r/w w atchdog timer clock selection flag (can be set only once after power application) wdtck0 flg 0.82h.0 r/w w atchdog timer clock selection flag (can be set only once after power application) wdtres flg 0.83h.3 r/w watchdog timer counter reset (when read: 0) dbfsp mem 0.84h r dbf stack pointer sprsel mem 0.85h r/w stack overflow/underflow reset selection flag (can be set only once after power application) ispres flg 0.85h.1 r/w stack overflow/underflow reset selection flag (can be set only once after power application) aspres flg 0.85h.0 r/w stack overflow/underflow reset selection flag (can be set only once after power application) cecnt3 flg 0.86h.3 r/w ce reset timer carry counter cecnt2 flg 0.86h.2 r/w ce reset timer carry counter cecnt1 flg 0.86h.1 r/w ce reset timer carry counter cecnt0 flg 0.86h.0 r/w ce reset timer carry counter movtsel1 flg 0.87h.1 r/w movt bit selection flag movtsel0 flg 0.87h.0 r/w movt bit selection flag sysrsp mem 0.88h r system register stack pointer sio2clc flg 0.8ah.3 r/w serial interface 2 clock level control flag sio2wrel flg 0.8ah.2 r/w serial interface 2 wait release control flag sio2wat1 flg 0.8ah.1 r/w serial interface 2 interrupt generation timing/wait control flag sio2wat0 flg 0.8ah.0 r/w serial interface 2 interrupt generation timing/wait control flag sio2cld flg 0.8bh.2 r serial interface 2 clock pin level detection flag sio2sic flg 0.8bh.1 r/w serial interface 2 interrupt source selection flag sio2svam flg 0.8bh.0 r/w serial interface 2 address mask function specification flag sio2cmdd flg 0.8ch.3 r serial interface 2 command signal detection flag sio2reld flg 0.8ch.2 r serial interface 2 bus release signal detection flag sio2cmdt flg 0.8ch.1 r/w serial interface 2 command signal trigger output control flag sio2relt flg 0.8ch.0 r/w serial interface 2 bus release signal trigger output control flag sio2bsye flg 0.8dh.3 r/w serial interface 2 synchronization busy signal enable flag sio2ackd flg 0.8dh.2 r serial interface 2 acknowledge detection flag sio2acke flg 0.8dh.1 r/w serial interface 2 acknowledge enable flag sio2ackt flg 0.8dh.0 r/w serial interface 2 acknowledge signal trigger output control flag sio2wup flg 0.8eh.3 r/w serial interface 2 wake-up function specification flag sio2md2 flg 0.8eh.2 r/w serial interface 2 operation mode selection flag sio2md1 flg 0.8eh.1 r/w serial interface 2 operation mode selection flag sio2md0 flg 0.8eh.0 r/w serial interface 2 clock direction selection flag
390 pd17717, 17718, 17719 data sheet u12330ej2v0ds symbol name attribute value r/w description sio2csie flg 0.8fh.3 r/w serial interface 2 operation enable/disable flag sio2coi flg 0.8fh.2 r coincidence signal detection flag from serial interface 2 address comparator sio2tcl1 flg 0.8fh.1 r/w serial interface 2 clock selection flag sio2tcl0 flg 0.8fh.0 r/w serial interface 2 clock selection flag pllscnf flg 0.90h.3 r/w swallow counter least significant bit setting flag pllmd1 flg 0.90h.1 r/w pll mode selection flag pllmd0 flg 0.90h.0 r/w pll mode selection flag pllrfck3 flg 0.91h.3 r/w pll reference frequency selection flag pllrfck2 flg 0.91h.2 r/w pll reference frequency selection flag pllrfck1 flg 0.91h.1 r/w pll reference frequency selection flag pllrfck0 flg 0.91h.0 r/w pll reference frequency selection flag pllul flg 0.92h.0 r&reset pll unlock ff flag beep1sel flg 0.93h.1 r/w beep1/general-purpose port pin function selection flag beep0sel flg 0.93h.0 r/w beep0/general-purpose port pin function selection flag beep1ck1 flg 0.94h.3 r/w beep1 clock selection flag beep1ck0 flg 0.94h.2 r/w beep1 clock selection flag beep0ck1 flg 0.94h.1 r/w beep0 clock selection flag beep0ck0 flg 0.94h.0 r/w beep0 clock selection flag wdtcy flg 0.96h.0 r watchdog timer/stack pointer reset status detection flag btm0cy flg 0.97h.0 r basic timer 0 carry flag btm0ck1 flg 0.98h.1 r/w basic timer 0 clock selection flag btm0ck0 flg 0.98h.0 r/w basic timer 0 clock selection flag sio3csie flg 0.9ah.3 r/w serial interface 3 operation enable/disable flag sio3hiz flg 0.9ah.2 r/w serial interface 3 so3 pin status setting flag sio3tcl1 flg 0.9ah.1 r/w serial interface 3 clock selection flag sio3tcl0 flg 0.9ah.0 r/w serial interface 3 clock selection flag sio3pe flg 0.9bh.2 r serial interface 3 parity error flag sio3fe flg 0.9bh.1 r serial interface 3 framing error flag sio3ove flg 0.9bh.0 r serial interface 3 overrun error flag sio3ps1 flg 0.9ch.3 r/w parity bit specification flag of uart sio3ps0 flg 0.9ch.2 r/w parity bit specification flag of uart sio3cl flg 0.9ch.1 r/w character length specification flag of uart sio3sl flg 0.9ch.0 r/w number of stop bits specification flag of uart transmission data sio3txe flg 0.9dh.3 r/w uart transmission mode enable flag sio3rxe flg 0.9dh.2 r/w uart reception mode enable flag sio3isrm flg 0.9dh.1 r/w reception completion interrupt enable flag in the case of error ieg4 flg 0.9eh.3 r/w edge direction selection flag for int4 pin interrupt request detection int4sel flg 0.9eh.2 r/w int4 pin interrupt request flag setting disable ieg3 flg 0.9eh.1 r/w edge direction selection flag for int3 pin interrupt request detection int3sel flg 0.9eh.0 r/w int3 pin interrupt request flag setting disable
391 pd17717, 17718, 17719 data sheet u12330ej2v0ds symbol name attribute value r/w description ieg2 flg 0.9fh.2 r/w edge direction selection flag for int2 pin interrupt request detection ieg1 flg 0.9fh.1 r/w edge direction selection flag for int1 pin interrupt request detection ieg0 flg 0.9fh.0 r/w edge direction selection flag for int0 pin interrupt request detection fcgch1 flg 0.0a0h.1 r/w fgc channel selection flag fcgch0 flg 0.0a0h.0 r/w fgc channel selection flag ifcgostt flg 0.0a1h.0 r if counter gate status detection flag (1: open, 0: closed) ifcmd1 flg 0.0a2h.3 r/w if counter mode selection flag (10: amif, 11: fcg) ifcmd0 flg 0.0a2h.2 r/w if counter mode selection flag (00: cgp, 11: fmif) ifcck1 flg 0.0a2h.1 r/w if counter clock selection flag ifcck0 flg 0.0a2h.0 r/w if counter clock selection flag ifcstrt flg 0.0a3h.1 w if counter count start flag ifcres flg 0.0a3h.0 w if counter reset flag adcch3 flg 0.0a4h.3 r/w a/d converter channel selection flag (dummy) adcch2 flg 0.0a4h.2 r/w a/d converter channel selection flag adcch1 flg 0.0a4h.1 r/w a/d converter channel selection flag adcch0 flg 0.0a4h.0 r/w a/d converter channel selection flag adcmd flg 0.0a5h.2 r/w a/d converter compare mode selection flag adcstt flg 0.0a5h.1 r a/d converter operation status detection flag (0: end of conversion, 1: conversion in progress) adccmp flg 0.0a5h.0 r a/d converter compare result detection flag pwmbit flg 0.0a6h.2 r/w pwm counter bit selection flag (0: 8 bits, 1: 9 bits) pwmck flg 0.0a6h.0 r/w pwm timer output clock selection flag pwm2sel flg 0.0a7h.2 r/w pwm2/general-purpose port pin function selection flag pwm1sel flg 0.0a7h.1 r/w pwm1/general-purpose port pin function selection flag pwm0sel flg 0.0a7h.0 r/w pwm0/general-purpose port pin function selection flag tm3sel flg 0.0a8h.3 r/w pwm/modulo timer 3 selection flag tm3en flg 0.0a8h.1 r/w modulo timer 3 count start flag tm3res flg 0.0a8h.0 r/w modulo timer 3 reset flag (when read: 0) tm2en flg 0.0a9h.3 r/w modulo timer 2 count start flag tm2res flg 0.0a9h.2 r/w modulo timer 2 reset flag (when read: 0) tm2ck1 flg 0.0a9h.1 r/w modulo timer 2 clock selection flag tm2ck0 flg 0.0a9h.0 r/w modulo timer 2 clock selection flag tm1en flg 0.0aah.3 r/w modulo timer 1 count start flag tm1res flg 0.0aah.2 r/w modulo timer 1 reset flag (when read: 0) tm1ck1 flg 0.0aah.1 r/w modulo timer 1 clock selection flag tm1ck0 flg 0.0aah.0 r/w modulo timer 1 clock selection flag tm0en flg 0.0abh.3 r/w modulo timer 0 count start flag tm0res flg 0.0abh.2 r/w modulo timer 0 reset flag (when read: 0) tm0ck1 flg 0.0abh.1 r/w modulo timer 0 clock selection flag tm0ck0 flg 0.0abh.0 r/w modulo timer 0 clock selection flag
392 pd17717, 17718, 17719 data sheet u12330ej2v0ds symbol name attribute value r/w description tm0ovf flg 0.0ach.3 r modulo timer 0 overflow detection flag tm0gceg flg 0.0ach.2 r/w modulo timer 0 gate close input signal edge selection flag tm0goeg flg 0.0ach.1 r/w modulo timer 0 gate open input signal edge selection flag tm0md flg 0.0ach.0 r/w modulo timer 0 modulo counter/gate counter selection flag ipsio3 flg 0.0adh.3 r/w serial interface 3 interrupt enable flag ipsio2 flg 0.0adh.2 r/w serial interface 2 interrupt enable flag iptm3 flg 0.0adh.1 r/w pwm timer interrupt enable flag iptm2 flg 0.0adh.0 r/w modulo timer 2 interrupt enable flag iptm1 flg 0.0aeh.3 r/w modulo timer 1 interrupt enable flag iptm0 flg 0.0aeh.2 r/w modulo timer 0 interrupt enable flag ip4 flg 0.0aeh.1 r/w int4 pin interrupt enable flag ip3 flg 0.0aeh.0 r/w int3 pin interrupt enable flag ip2 flg 0.0afh.3 r/w int2 pin interrupt enable flag ip1 flg 0.0afh.2 r/w int1 pin interrupt enable flag ip0 flg 0.0afh.1 r/w int0 pin interrupt enable flag ipce flg 0.0afh.0 r/w ce pin interrupt enable flag irqsio3 flg 0.0b4h.0 r/w serial interface 3 interrupt request detection flag irqsio2 flg 0.0b5h.0 r/w serial interface 2 interrupt request detection flag irqtm3 flg 0.0b6h.0 r/w pwm timer interrupt request detection flag irqtm2 flg 0.0b7h.0 r/w modulo timer 2 interrupt request detection flag irqtm1 flg 0.0b8h.0 r/w modulo timer 1 interrupt request detection flag irqtm0 flg 0.0b9h.0 r/w modulo timer 0 interrupt request detection flag int4 flg 0.0bah.3 r int4 pin status detection flag irq4 flg 0.0bah.0 r/w int4 pin interrupt request detection flag int3 flg 0.0bbh.3 r int3 pin status detection flag irq3 flg 0.0bbh.0 r/w int3 pin interrupt request detection flag int2 flg 0.0bch.3 r int2 pin status detection flag irq2 flg 0.0bch.0 r/w int2 pin interrupt request detection flag int1 flg 0.0bdh.3 r int1 pin status detection flag irq1 flg 0.0bdh.0 r/w int1 pin interrupt request detection flag int0 flg 0.0beh.3 r int0 pin status detection flag irq0 flg 0.0beh.0 r/w int0 pin interrupt request detection flag ce flg 0.0bfh.3 r ce pin status detection flag cecntstt flg 0.0bfh.1 r ce reset counter status detection flag irqce flg 0.0bfh.0 r/w ce pin interrupt request detection flag p0dpld3 flg 15.66h.3 r/w p0d3 pin pull-down resistor selection flag p0dpld2 flg 15.66h.2 r/w p0d2 pin pull-down resistor selection flag p0dpld1 flg 15.66h.1 r/w p0d1 pin pull-down resistor selection flag p0dpld0 flg 15.66h.0 r/w p0d0 pin pull-down resistor selection flag
393 pd17717, 17718, 17719 data sheet u12330ej2v0ds symbol name attribute value r/w description p3dgio flg 15.67h.3 r/w p3d input/output selection flag p3cgio flg 15.67h.2 r/w p3c input/output selection flag p3bgio flg 15.67h.1 r/w p3b input/output selection flag p3agio flg 15.67h.0 r/w p3a input/output selection flag p2dbio3 flg 15.68h.3 r/w p2d3 input/output selection flag (dummy) p2dbio2 flg 15.68h.2 r/w p2d2 input/output selection flag p2dbio1 flg 15.68h.1 r/w p2d1 input/output selection flag p2dbio0 flg 15.68h.0 r/w p2d0 input/output selection flag p2cbio3 flg 15.69h.3 r/w p2c3 input/output selection flag p2cbio2 flg 15.69h.2 r/w p2c2 input/output selection flag p2cbio1 flg 15.69h.1 r/w p2c1 input/output selection flag p2cbio0 flg 15.69h.0 r/w p2c0 input/output selection flag p2bbio3 flg 15.6ah.3 r/w p2b3 input/output selection flag p2bbio2 flg 15.6ah.2 r/w p2b2 input/output selection flag p2bbio1 flg 15.6ah.1 r/w p2b1 input/output selection flag p2bbio0 flg 15.6ah.0 r/w p2b0 input/output selection flag p2abio3 flg 15.6bh.3 r/w p2a3 input/output selection flag (dummy) p2abio2 flg 15.6bh.2 r/w p2a2 input/output selection flag p2abio1 flg 15.6bh.1 r/w p2a1 input/output selection flag p2abio0 flg 15.6bh.0 r/w p2a0 input/output selection flag p1dbio3 flg 15.6ch.3 r/w p1d3 input/output selection flag p1dbio2 flg 15.6ch.2 r/w p1d2 input/output selection flag p1dbio1 flg 15.6ch.1 r/w p1d1 input/output selection flag p1dbio0 flg 15.6ch.0 r/w p1d0 input/output selection flag p0cbio3 flg 15.6dh.3 r/w p0c3 input/output selection flag p0cbio2 flg 15.6dh.2 r/w p0c2 input/output selection flag p0cbio1 flg 15.6dh.1 r/w p0c1 input/output selection flag p0cbio0 flg 15.6dh.0 r/w p0c0 input/output selection flag p0bbio3 flg 15.6eh.3 r/w p0b3 input/output selection flag p0bbio2 flg 15.6eh.2 r/w p0b2 input/output selection flag p0bbio1 flg 15.6eh.1 r/w p0b1 input/output selection flag p0bbio0 flg 15.6eh.0 r/w p0b0 input/output selection flag p0abio3 flg 15.6fh.3 r/w p0a3 input/output selection flag p0abio2 flg 15.6fh.2 r/w p0a2 input/output selection flag p0abio1 flg 15.6fh.1 r/w p0a1 input/output selection flag p0abio0 flg 15.6fh.0 r/w p0a0 input/output selection flag
394 pd17717, 17718, 17719 data sheet u12330ej2v0ds 23.5 peripheral hardware registers symbol name attribute value r/w description adcr dat 02h r/w a/d converter reference voltage setting register sio2sfr dat 03h r/w presettable shift register 2 sio2sva dat 04h r/w serial interface 2 slave address register sio3txs dat 05h w serial interface 3 transmission register sio3rxb dat 05h r serial interface 3 receive buffer register tm0m dat 1ah r/w timer modulo 0 register tm0c dat 1bh r timer modulo 0 counter tm1m dat 1ch r/w timer modulo 1 register tm1c dat 1dh r timer modulo 1 counter tm2m dat 1eh r/w timer modulo 2 register tm2c dat 1fh r timer modulo 2 counter ar dat 40h r/w address register dbfstk dat 41h r/w dbf stack register pllr dat 42h r/w pll data register ifc dat 43h r if counter data register pwmr0 dat 44h r/w pwm0 data register pwmr1 dat 45h r/w pwm1 data register pwmr2 dat 46h r/w pwm2 data register tm3m dat 46h r/w timer modulo 3 register 23.6 others symbol name attribute value description dbf dat 0fh operand of get/put/movt/movth/movl instruction (dbf) ix dat 01h operand of inc instruction (ix) ar_epa1 dat 8040h operand of call/br/movt/movth/movtl instruction (epa bit on) ar_epa0 dat 4040h operand of call/br/movt/movth/movtl instruction (epa bit off)
395 pd17717, 17718, 17719 data sheet u12330ej2v0ds 24. electrical characteristics absolute maximum ratings (t a = 25 c) parameter symbol condition rating unit supply voltage v dd 0.3 to +6.0 v input voltage v i other than ce, int0 through int4, and reset pins 0.3 to v dd +0.3 v ce, int0 through int4, and reset pins 0.3 to v dd +0.6 v output voltage v o except p1b0 through p1b3 0.3 to v dd +0.3 v high-level output current i oh 1 pin 8.0 ma total of p2a0 through p2a2, p3a0 through p3a3, 15.0 ma and p3b0 through p3b3 total of p0a0, p0a1, p0b0 through p0b3, 25.0 ma p0c0 through p0c3, p1d0 through p1d3, p2b0 through p2b3, p2c0 through p2c3, p2d2, p3c0 through p3c3, and p3d0 through p3d3 low-level output current i ol 1 pin of p1b0 through p1b3 12.0 ma 1 pin of p1b0 through p1b3 8.0 ma total of p2a0 through p2a2, p3a0 through p3a3, 15.0 ma and p3b0 through p3b3 total of p0a0 through p0a3, p0b0 through p0b3, 25.0 ma p0c0 through p0c3, p1d0 through p1d3, p2b0 through p2b3, p2c0 through p2c3, p2d0 through p2d2, p3c0 through p3c3, and p3d0 through p3d3 total of p1b0 through p1b3 pins 25.0 ma output voltage v bds p1b0-p1b3 14.0 v total power dissipation p t 200 mw operating ambient t a 40 to +85 c temperature storage temperature t stg 55 to +125 c caution if the rated value of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. the absolute maximum ratings define the rated values exceeding which the product may be physically damaged. never exceed these ratings. recommended operating range (t a = 40 to +85 c) parameter symbol condition min. typ. max. unit supply voltage v dd1 when cpu and pll are operating 4.5 5.0 5.5 v v dd2 when cpu and pll are stopped 3.5 5.0 5.5 v recommended output voltage (t a = 40 to +85 c) parameter symbol condition min. typ. max. unit output voltage v bds p1b0-p1b3 12 v
396 pd17717, 17718, 17719 data sheet u12330ej2v0ds dc characteristics (t a = 40 to +85 c, v dd = 3.5 to 5.5 v) parameter symbol condition min. typ. max. unit supply current i dd1 when cpu is operating and pll is stopped with 1.5 3.0 ma sine wave input to x in pin. (f in = 4.5 mhz 1%, v in = v dd ) i dd2 when cpu and pll are stopped with sine wave 0.7 1.5 ma input to x in pin. (f in = 4.5 mhz 1%, v in = v dd ) with halt instruction data retention voltage v ddr1 crystal oscillation 3.5 5.5 v v ddr2 crystal power failure detection by timer ff 2.2 5.5 v v ddr3 oscillation stops data memory retained 2.0 5.5 v data retention current i ddr1 crystal v dd = 5 v, t a = 25 c 2.0 4.0 a i ddr2 oscillation stops 2.0 30.0 a high-level input voltage v ih1 p0a0, p0b1, p0c0-p0c3, p1a0, p1a1, p1c0-p1c3, 0.7v dd v dd v p1d0-p1d3, p2a2, p2b0-p2b3, p2c0-p2c3, p3a0-p3a3, p3b0-p3b3, p3c0-p3c3, p3d0-p3d3 v ih2 p0a1-p0a3, p0b0, p0b2, p0b3, p2a0, p2a1, 0.8v dd v dd v p2d0-p2d2, ce, int0-int4, reset v ih3 p0d0-p0d3 0.55v dd v dd v low-level input voltage v il1 p0a0, p0b1, p0c0-p0c3, p1a0, p1a1, p1c0-p1c3, 0 0.3v dd v p1d0-p1d3, p2a2, p2b0-p2b3, p2c0-p2c3, p3a0-p3a3, p3b0-p3b3, p3c0-p3c3, p3d0-p3d3 v il2 p0a1-p0a3, p0b0, p0b2, p0b3, p2a0, p2a1, 0 0.2v dd v p2d0-p2d2, ce, int0-int4, reset v il3 p0d0-p0d3 0 0.15v dd v high-level output current i oh1 p0a0, p0a1, p0b0-p0b3, p0c0-p0c3, p1d0-p1d3, 1.0 ma p2a0-p2a2, p2b0-p2b3, p2c0-p2c3, p2d2, p3a0-p3a3, p3b0-p3b3, p3c0-p3c3, p3d0-p3d3 v oh = v dd 1 v i oh2 eo0, eo1 v dd = 4.5 to 5.5 v, v oh = v dd 1 v 3.0 ma low-level output current i ol1 p0a0-p0a3, p0b0-p0b3, p0c0-p0c3, p1d0-p1d3, 1.0 ma p2a0-p2a2, p2b0-p2b3, p2c0-p2c3, p2d0-p2d2, p3a0-pa3a, p3b0-p3b3, p3c0-p3c3, p3d0-p3d3 v ol = 1 v i ol2 eo0, eo1 v dd = 4.5 to 5.5 v, v ol = 1 v 3.0 ma i ol3 p1b0-p1b3 v ol = 1 v 7.0 ma high-level input current i ih p0d0 through p0d3 pulled down v in = v dd 5.0 150 a output off leakage i lo1 p1b0-p1b3 v in = 12 v 1.0 a current i lo2 eo0, eo1 v in = v dd , v in = 0 v 1.0 a high-level input leakage i lih input pin v in = v dd 1.0 a current low-level input leakage i lil input pin v in = 0 v 1.0 a current
397 pd17717, 17718, 17719 data sheet u12330ej2v0ds ac characteristics (t a = 40 to +85 c, v dd = 5 v 10%) parameter symbol condition min. typ. max. unit operating frequency f in1 vcol pin, mf mode, sine wave input 0.5 3 mhz v in = 0.1 v p-p note f in2 vcol pin, hf mode, sine wave input 10 40 mhz v in = 0.1 v p-p note f in3 vcoh pin, vhf mode, sine wave input 60 130 mhz v in = 0.1 v p-p note f in4 amifc pin, sine wave input 0.4 0.5 mhz v in = 0.15 v p-p note f in5 fmifc pin, fmif count mode, sine wave input 10 11 mhz v in = 0.20 v p-p f in6 fmifc pin, amif count mode, sine wave input 0.4 0.5 mhz v in = 0.15 v p-p sio2 input frequency f in7 external clock 1 mhz sio3 input frequency f in8 external clock 0.7 mhz note the condition of sine wave input v in = 0.1 v p-p is the rated value when the pd17717, 17718, or 17719 alone is operating. where influence of noise must be taken into consideration, operation under input amplitude condition of v in = 0.15 v p-p is recommended. a/d converter characteristics (t a = 40 to +85 c, v dd = 5 v 10%) parameter symbol condition min. typ. max. unit a/d conversion total error 8 bit 3.0 lsb a/d conversion total error 8 bit t a = 0 to 85 c 2.5 lsb reference characteristics (t a = +25 c, v dd = 5.0 v) parameter symbol condition min. typ. max. unit supply current i dd3 when cpu and pll are operating with sine wave 6.0 12.0 ma input to vcoh pin (f in = 130 mhz, v in = 0.3 v p-p )
398 pd17717, 17718, 17719 data sheet u12330ej2v0ds 25. package drawing 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.2 0.4 14.0 0.2 0.13 0.825 i 17.2 0.4 j c 14.0 0.2 h 0.30 0.10 0.65 (t.p.) k 1.6 0.2 l 0.8 0.2 f 0.825 s80gc-65-3b9-6 n p q 0.10 2.7 0.1 0.1 0.1 r s 5 5 3.0 max. m 0.15 + 0.10 ? 0.05 60 61 40 80 1 21 20 41 s s n j detail of lead end c d a b r k m l p i s q g f m h
399 pd17717, 17718, 17719 data sheet u12330ej2v0ds 26. recommended soldering conditions solder the pd17719 under the following recommended conditions. for the details of the recommended soldering conditions, refer to ?emiconductor device mounting technology manual (c10535e) . for the soldering method and conditions other than those recommended, consult nec. table 26-1. soldering conditions of surface mount type pd17717gc-xxx-3b9: 80-pin plastic qfp (14 x 14) pd17718gc-xxx-3b9: 80-pin plastic qfp (14 x 14) pd17719gc-xxx-3b9: 80-pin plastic qfp (14 x 14) symbol of soldering method soldering condition recommended condition infrared reflow package peak temperature: 235 c, time: 30 seconds max. (210 c min.) ir35-00-3 number of times: 3 max. vps package peak temperature: 215 c, time: 40 seconds max. (200 c min.) vp15-00-3 number of times: 3 max. wave soldering soldering bath temperature: 260 c max., time: 10 seconds max., number of times: 1, ws60-00-1 preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per side of device) caution do not use two or more soldering methods in combination (except partial heating method).
400 pd17717, 17718, 17719 data sheet u12330ej2v0ds appendix a. cautions on connecting crystal resonator when using the system clock oscillation circuit, wire the portion enclosed by the dotted line in the figure below as follows to prevent adverse influence from wiring capacity. keep the wiring length as short as possible. if capacitances c1 and c2 are too high, the oscillation start characteristics may be degraded or current consumption may increase. generally, connect a trimmer capacitor for adjusting the oscillation frequency to the x in pin. depending on the crystal resonator to be used, however, the oscillation stability differs. therefore, evaluate the crystal resonator actually used. the crystal oscillation frequency cannot be accurately adjusted when an emulation probe is connected to the x out and x in pin, because of the capacitance of the probe. adjust the frequency while measuring the vco oscillation frequency. pd17717 pd17718 pd17719 4.5-mhz crystal resonator c1 c2 x out x in
401 pd17717, 17718, 17719 data sheet u12330ej2v0ds appendix b. development tools the following development tools are available for development of programs for the pd17719. hardware name outline ie-17k, ie-17k-et, and emu-17k are in-circuit emulators that can be used with any model in the 17k series. ie-17k and ie-17k-et are connected to a host machine, which is pc-9800 series or ibm pc/at tm , with rs-232c. emu-17k is mounted to the expansion slot of a host machine, pc-9800 series. by using these in-circuit emulators with a system evaluation board (se board) corresponding to each model, these emulators operate dedicated to the model. when man-machine interface software simplehost tm is used, a more sophisticated debugging environment can be created. emu-17k also has a function to allow you to check the contents of the data memory real-time. se-17709 is an se board for the pd17719 subseries. this board can be used alone to evaluate a system, or in combination with an in-circuit emulator for debugging. ep-17k80gc is an emulation probe for the pd17719 subseries. by using this probe with ev- 9200gc-80 note 3 , the se board and target system are connected. ev-9200gc-80 is a conversion socket for 80-pin plastic qfp (14 x 14). it is used to connect ep- 17k80gc and target system. pg-1500 is a prom programmer supporting pd17p719. it can program pd17p719 when connected with pg-1500 adapter pa-17kdz and programmer adapter pa-17p709gc. pa-17p709gc is an adapter to program pd17p719. it is used with pg-1500. notes 1. low-price model: external power supply type 2. this is a product of naito densei machida mfg. co., ltd. for details, consult naito densei machida mfg. 5co., ltd. ((045) 475-4191). 3. one ev-9200gc-80 is supplied with the ep-17k80gc. five ev-9200gc-80 are also available as a set. remark third party prom programmers af-9703, af-9704, af-9705, and af-9706 are available from ando electric co., ltd. use these programmers with programmer adapter pa-17p709gc. for details, consult ando electric co., ltd. ((03) 3733-1163). in-circuit emulator ie-17k ie-17k-et note 1 emu-17k note 2 se board (se-17709) emulation probe (ep-17k80gc) conversion socket (ev-9200gc-80 note 3 ) prom programmer (pg-1500) programmer adapter (pa-17p709gc)
402 pd17717, 17718, 17719 data sheet u12330ej2v0ds software name outline host machine os supply order code media pc-9800 series japanese 3.5"2hd saa13ra17k windows tm ibm pc/at- japanese 3.5"2hc sab13ra17k compatible windows english sbb13ra17k windows pc-9800 series japanese 3.5"2hd saa13as17707 windows ibm pc/at- japanese 3.5"2hc sab13as17707 compatible windows english sbb13as17707 windows pc-9800 series japanese 3.5"2hd saa13id17k windows ibm pc/at- japanese 3.5"2hc sab13id17k compatible windows english sbb13id17k windows 17k assembler (ra17k) device file (as17707) support software ( simplehost ) ra17k is an assembler common to the 17k series products. to develop the program of the pd17719, the ra17k is used in combination with the device file. as17707 is a device file for the pd17719 subseries. it is used in combination with an assembler common to the 17k series (ra17k). simplehost is software that serves as a human interface on windows for program development using an in-circuit emulator and personal computer.
403 pd17717, 17718, 17719 data sheet u12330ej2v0ds [memo]
404 pd17717, 17718, 17719 data sheet u12330ej2v0ds notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
405 pd17717, 17718, 17719 data sheet u12330ej2v0ds regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-3067-5800 fax: 01-3067-5899 nec electronics (france) s.a. madrid office madrid, spain tel: 091-504-2787 fax: 091-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.2
pd17717, 17718, 17719 simplehost is a trademark of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of ibm corporation. purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00. 4 the information in this document is current as of may, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

▲Up To Search▲

Price & Availability of UPD17717GC-XXX-3B9

	To Download UPD17717GC-XXX-3B9 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .